S1D13704 Epson Electronics America, Inc., S1D13704 Datasheet - Page 76

• Manufacturer Part Number: S1D13704
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 70
bits 1-0
bits 7-0
REG[1Eh] and REG[1Fh]
S1D13704
X26A-A-001-06
REG[1Ch] Line Byte Count Register for SwivelView Mode
Address = FFFCh
Count bit 7
Line Byte
Count bit 6
Line Byte
Mode Enable
(REG[1Bh] bit 7)
SwivelView
0
1
1
1
1
1
1
1
1
SwivelView Mode Pixel Clock Select Bits [1:0]
These two bits select the Pixel Clock (PCLK) source in SwivelView Mode - these bits
have no effect in Landscape Mode. The following table shows the selection of PCLK and
MCLK in SwivelView Mode - see Section 12, “SwivelView™” on page 80 for details.
Line Byte Count Bits [7:0]
This register is the byte count from the beginning of one line to the beginning of the next
consecutive line (commonly called “stride” by programmers). This register may be used to
create a virtual image in SwivelView mode.
REG[1Eh] and REG[1Fh] are reserved for factory S1D13704 testing and should not be
written. Any value written to these registers may result in damage to the S1D13704 and/or
any panel connected to the S1D13704.
Count bit 5
Line Byte
Table 8-9: Selection of PCLK and MCLK in SwivelView Mode
(REG[1Bh] bit 6)
Mode Select
SwivelView
X
0
0
0
0
1
1
1
1
Count bit 4
Line Byte
Pixel Clock (PCLK) Select
Where CLK is CLKI (REG[02h] bit 4 = 0) or CLKI/2 (REG[02h] bit 4 = 1)
Bit 1
(REG[1Bh] bits [1:0]
X
0
0
1
1
0
0
1
1
Count bit 3
Line Byte
Bit 0
X
0
1
0
1
0
1
0
1
Count bit 2
Line Byte
PCLK =
CLK/2
CLK/4
CLK/8
CLK/2
CLK/2
CLK/4
CLK/8
CLK
CLK
Epson Research and Development
Hardware Functional Specification
Count bit
Line Byte
Vancouver Design Center
See Reg[02h] bit 5
1
Issue Date: 02/02/01
MCLK =
Read/Write
CLK/2
CLK/4
CLK/8
CLK/2
CLK/4
Count bit
CLK
CLK
CLK
Line Byte
0