S1D13704 Epson Electronics America, Inc., S1D13704 Datasheet - Page 337

• Manufacturer Part Number: S1D13704
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

EPSON Research and Development
Vancouver Design Center
2.2 Memory Mapping and Aliasing
2.3 S1D13704 Configuration and Pin Mapping
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 01/02/12
Configuration
S1D13704
CNF[2:0]
CNF3
BS#
Pin
= configuration for Toshiba TX3912 host bus interface
Note
The S1D13704 requires an addressing space of 64K bytes. The on-chip display memory occupies
the range 0 through 9FFFh. The registers occupy the range FFE0h through FFFFh. The TX3912
demultiplexed address lines A16 and above are ignored, thus the S1D13704 is aliased 1024 times at
64K byte intervals over the 64M byte PC Card slot #1 memory space. In this example
implementation, the TX3912 control signal CARDREG* is ignored, the S1D13704 also takes up the
entire PC Card slot 1 configuration space.
The S1D13704 is configured at power up by latching the state of the CNF[4:0] pins. Pin BS# also
plays a role in host bus interface configuration. For details on configuration, refer to the S1D13704
Hardware Functional Specification, document number X26A-A-001-xx.
The table below shows those configuration settings relevant to the direct connection approach.
When the S1D13704 is configured for “Generic #2” interface, the host interface pins are mapped as
in the table below.
If aliasing is undesirable, additional decoding circuitry must be added.
Table 2-2: S1D13704 Generic #2 Interface Pin Mapping
Table 2-1: S1D13704 Configuration for Direct Connection
Generic #2
Big Endian
1 (IO V
Value hard wired on this pin is used to configure:
DD
Pin Name
)
RD/WR#
WE1#
WE0#
RD#
BS#
Connect to IO V
Connect to IO V
111: Generic #1 or #2
Pin Function
BHE#
WE#
RD#
DD
DD
Little Endian
Generic #1
0 (V
SS
)
X26A-G-004-02
S1D13704
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