S1D13704 Epson Electronics America, Inc., S1D13704 Datasheet - Page 192

• Manufacturer Part Number: S1D13704
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 14
S1D13704
X26A-B-001-03
Panel Dimensions
Non-Display Periods
Timings
TFT/FPLINE
Frame Rate
Pixel Clock
Start Pos
These fields specify the panel width and height. A
number of common widths and height are available in
the selection boxes. If the width/height of your panel is
not listed, enter the actual panel dimensions into the edit
field.
Manually entered widths must be multiples of 8 pixels.
If a value is entered that does not match these require-
ments, a notification box appears and 13704CFG
rounds up the value to the next allowable width.
It is recommended that these automatically generated
non-display values be used without adjustment.
However, manual adjustment may be useful in fine
tuning the non-display width and non-display height.
These settings show the Frame Rate and Pixel Clock
timings.
This field displays the effective frame rate of the LCD
panel. Panel dimensions are fixed therefore frame rate
can only be adjusted by changing either PCLK or non-
display period values. Higher frame rates correspond to
smaller horizontal and vertical non-display values, or
higher PCLK frequencies.
The pixel clock used for the LCD panel is displayed in
this field. The pixel clock is dependent on the CLKI
source.
Specifies the delay (in pixels) from the start of the
horizontal non-display period to the leading edge of the
FPLINE pulse. This setting is only available when the
selected panel type is TFT.
Refer to S1D13704 Hardware Functional Specifi-
cation, document number X26A-A-001-xx for a
complete description of the FPLINE pulse settings.
Epson Research and Development
13704CFG Configuration Program
Vancouver Design Center
Issue Date: 02/03/11