S1D13704 Epson Electronics America, Inc., S1D13704 Datasheet - Page 38

• Manufacturer Part Number: S1D13704
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 32
7.1.5 Generic #1 Interface Timing
S1D13704
X26A-A-001-06
WE0#,WE1#
RD0#, RD1#
A[16:0]
Symbol
D[15:0]
BCLK
D[15:0]
WAIT#
(write)
T
f
(read)
BCLK
BCLK
t10
t11
CS#
t1
t2
t3
t4
t5
t6
t7
t8
t9
Bus Clock frequency
Bus Clock period
A[15:0], CS# valid to WE0#, WE1# low (write cycle) or RD0#, RD1# low (read
cycle)
WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to A[15:0],
CS# invalid
WE0#, WE1# low to D[15:0] valid (write cycle)
RD0#, RD1# low to D[15:0] driven (read cycle)
WE0#, WE1# high to D[15:0] invalid (write cycle)
D[15:0] valid to WAIT# high (read cycle)
RD0#, RD1# high to D[15:0] high impedance (read cycle)
WE0#, WE1# low (write cycle) or RD0#, RD1# low (read cycle) to WAIT#
driven low
BCLK to WAIT# high
WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to WAIT#
high impedance
WAIT# high to WE0#, WE1#, RD0#, RD1# high
T
BCLK
Hi-Z
Hi-Z
Hi-Z
t1
Note
BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 87
t8
t3
t4
Figure 7-5: Generic #1 Timing
Table 7-5: Generic #1 Timing
Parameter
VALID
t9
VALID
t6
t11
Epson Research and Development
VALID
1/f
1T
Min
Hardware Functional Specification
BCLK
BCLK
0
0
0
0
0
Vancouver Design Center
T
Max
BCLK
50
17
10
16
16
11
Issue Date: 02/02/01
t2
t5
t10
t7
Units
MHz
MHz
Hi-Z
Hi-Z
ns
ns
ns
ns
ns
ns
ns
ns
ns