S1D13704 Epson Electronics America, Inc., S1D13704 Datasheet - Page 307

• Manufacturer Part Number: S1D13704
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
3.2 Configuration Jumpers
S5U13704B00C Rev. 2.0 Evaluation Board User Manual
Issue Date: 2002/09/16
Jumper
JP1
JP2
JP3
JP4
JP5
JP7
= Required settings when used with PCI Bridge FPGA
LCD Panel Voltage Selection
BS# Signal Selection
Bus Clock Selection
PCI Bridge FPGA
IOVDD Selection
CLKI Selection
Function
Note
The S5U13704B00C has six jumper blocks which configure various setting on the board.
The jumper positions for each function are shown below.
JP1 - IOVDD Selection
JP1 selects the IOVDD voltage for S1D13704.
When the jumper is in position 1-2, IOVDD is 3.3V. This settings must be used for a 3.3V
host CPU system.
When the jumper is in position 2-3, IOVDD is 5.0V. This setting must be used for a 5.0V
host CPU system.
For PCI host, JP1 can be set in either position.
Figure 3-2: Configuration Jumper (JP1) Location
Disabled for non-PCI host
Pulled Down to GND (for
External Oscillator (U7)
External Oscillator (U2)
Generic #1 Interface)
Table 3-2: Jumper Summary
+3.3V LCDVCC
+3.3V IOVDD
Position 1-2
Pulled High to IOVDD (for
3.3 Volt
IOVDD
Generic #2 Interface)
JP1
From Host CPU
+5.0V LCDVCC
+5.0V IOVDD
Position 2-3
BCLK
n/a
5.0 Volt
IOVDD
For SH-3, SH-4, MC68k #1
Enabled for PCI host
and MC68K #2 bus
No Jumper
n/a
n/a
n/a
n/a
X26A-G-014-02
S1D13704
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