S1D13704 Epson Electronics America, Inc., S1D13704 Datasheet - Page 336
S1D13704
Manufacturer Part Number
S1D13704
Description
LCD Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D13704.pdf
(492 pages)
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2 Direct Connection to the Toshiba TX3912
2.1 General Description
S1D13704
X26A-G-004-02
ENDIAN
CARD1WAIT*
CARD1CSH*
CARD1CSL*
DCLKOUT
TX3912
D[31:24]
D[23:16]
A[12:0]
RD*
WE*
ALE
In this example implementation, the S1D13704 occupies the TX3912 PC Card slot #1.
The S1D13704 is easily interfaced to the TX3912 with minimal additional logic. The address bus of
the TX3912 PC Card interface is multiplexed and can be demultiplexed using an advanced CMOS
latch (e.g., 74ACT373). The direct connection approach makes use of the S1D13704 in its “Generic
Interface #2” configuration.
The following diagram demonstrates a typical implementation of the interface.
The “Generic #2” host interface control signals of the S1D13704 are asynchronous with respect to
the S1D13704 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13704 clock frequencies.
The S1D13704 also has internal clock dividers providing additional flexibility.
Figure 2-1: S1D13704 to TX3912 Direct Connection
Latch
V
DD
Clock divider
pull-up
...or...
Oscillator
System RESET
Interfacing to the Toshiba MIPS TX3912 Processor
IO V
IO V
+3.3V
DD
DD
See text
EPSON Research and Development
BS#
RD/WR#
IO V
RD#
WE#
BHE#
CLKI
BCLK
RESET#
CS#
AB[15:13]
AB[12:0]
DB[7:0]
DB[15:8]
WAIT#
S1D13704
DD
, CORE V
Vancouver Design Center
Issue Date: 01/02/12
DD
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