S1D13704 Epson Electronics America, Inc., S1D13704 Datasheet - Page 39

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S1D13704

Manufacturer Part Number
S1D13704
Description
LCD Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

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Epson Research and Development
Vancouver Design Center
7.1.6 Generic #2 Interface Timing
Hardware Functional Specification
Issue Date: 02/02/01
WE#,RD#
A[16:0]
D[15:0]
Symbol
D[15:0]
BHE#
(write)
WAIT#
T
BCLK
f
(read)
BCLK
BCLK
t10
t11
CS#
t1
t2
t3
t4
t5
t6
t7
t8
t9
Bus Clock frequency
Bus Clock period
A[15:0], BHE#, CS# valid to WE#, RD# low
WE#, RD# high to A[15:0], BHE#, CS# invalid
WE# low to D[15:0] valid (write cycle)
WE# high to D[15:0] invalid (write cycle)
RD# low to D[15:0] driven (read cycle)
D[15:0] valid to WAIT# high (read cycle)
RD# high to D[15:0] high impedance (read cycle)
WE#, RD# low to WAIT# driven low
BCLK to WAIT# high
WE#, RD# high to WAIT# high impedance
WAIT# high to WE#, RD# high
T
BCLK
Hi-Z
Hi-Z
Hi-Z
t1
Note
BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 87
t8
t3
t5
Figure 7-6: Generic #2 Timing
Table 7-6: Generic #2 Timing
Parameter
VALID
t9
VALID
t6
t11
VALID
1/f
1T
Min
BCLK
BCLK
0
0
0
0
0
T
Max
BCLK
50
16
10
14
16
11
t2
t4
t10
t7
X26A-A-001-06
S1D13704
Units
MHz
Hi-Z
Hi-Z
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 33

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