S1D13704 Epson Electronics America, Inc., S1D13704 Datasheet - Page 380

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S1D13704

Manufacturer Part Number
S1D13704
Description
LCD Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

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Page 12
S1D13704
X26A-G-008-05
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus inter-
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. This signal is active low and may need to be
inverted if the host CPU wait state signal is active high.
face for Generic #2 mode. However, BS# is used to configure the S1D13704 for
Generic #2 mode and should be tied high (connected to IO V
be tied high.
Interfacing to the NEC VR4102™ Microprocessor
Epson Research and Development
DD
). RD/WR# should also
Vancouver Design Center
Issue Date: 01/02/12

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