PM5364 pmc-sierra, PM5364 Datasheet - Page 193

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
2. Write the desired configuration to the Indirect Data Register #1.
3. Write the Indirect Tributary Address register, setting the RWB bit low and setting the
4. Return to step 1 to configure another tributary.
Interrupt Service Routine
Each tributary within the TASR has an interrupt bit for the signal fail (SF) alarm. The interrupt
sources for SF are summarized in Table 15.
The TASR generates TRIB_INT[X][Y][Z] interrupts based on transitions in the value of
tributaries’ SFV register bit. When the SFV register bit for a tributary transitions from either 1 to
0 or 0 to 1, the TRIB_INT[X][Y][Z] interrupt is generated.
If the SFE bit of the TASR Indirect Data Register #1 is programmed to logic 1 and the SFV bit
transition occurs, the corresponding TRIB_INT[X][Y][Z] interrupt status bit will get asserted.
The device INTB output will be asserted if the INTE bit of the TASR configuration register is
set to logic 1. The contribution of interrupts from the TASR block to the device INTB will be
masked if the INTE bit is a logic 0.
Note that the device INTB pin and TASR TRIB_INT[X][Y][Z] register bits will not become
asserted if the SFE enable bit is asserted after the SFV transition occurs. The SFE interrupt
enable bit must be set to logic 1 before the SFV changes status.
Once a device interrupt has been asserted as a result of a TASR interrupt, the TASR interrupt
can only be cleared by clearing the TRIB_INT[X][Y][Z] interrupt status register bits.
TRIB_INT[X][Y][Z] register bits are write-one-to-clear bits. In other words, to clear a
TRIB_INT[X][Y][Z] register bit, the user must write a logic 1 to the register bit. Note also that
the interrupt bits within the TASR Interrupt Source #1 and TASR Interrupt Source #2 registers
clear automatically and instantaneously when the corresponding TRIB_INT[X][Y][Z] bit (or
bits) are cleared.
To aid in quick identification of interrupts, the TASR provides a hierarchy of interrupt summary
bits . Using the interrupt summary bits to guide the search, an interrupt on any of the 336
tributaries is identifiable with 2 steps. To do so, first identify the register containing the tributary
interrupt summary bit by reading the Interrupt Source #1 and the Interrupt Source #2 registers.
Next, identify which tributary is generating the interrupt by reading the appropriate STM-0 #X
Interrupt Status register.
STM1, TUG3, TUG2, and TU bits to the desired values. (The data written in step 2 will
take effect for the selected tributary once the BUSY in the Indirect Tributary Address
register bit deasserts.)
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Released
193