PM5364 pmc-sierra, PM5364 Datasheet - Page 92

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

10.3.3
10.3.4
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
Table 6 Serial TelecomBus Character Encoding
MUX_FIFO Block
The MUX_FIFO block converts four STS-12 flows to a single STS-48 equivalent flow. Figure
16 shows the flow but in reverse order. It is used in the STS-48 slice only. The egress STSI
block shall be set in OC-48 to OC-12 mode. It is not used when the STS-48 block is used in
either of the STS-12 modes.
When transmitting in STS-48 mode the four STS-12 equivalent flows received synchronous to
77MHz REFCLK are interleaved from channel 1 to channel #4. This generates an output flow
synchronous to the SERDES generated 311MHz clock (four times faster than 77MHz). The J0
marker received for the STS-12 equivalent input flow is retimed and marks the J0 position of
channel 1 in the STS-48 equivalent output flow.
TSEC_SLICE Block
The TSEC_SLICE block contains the TSEC functional block followed by a timing FIFO. The
FIFO decouples phase, jitter and wander between the core clock, which clocks data into the
FIFO from the TSEC, and the SERDES generated transmit clock, which clocks data out of the
FIFO into the SERDES.
Transmit Data Scrambler 8B/10B Encoder (TSEC)
The TSEC operates in either Serial TelecomBus mode or in SONET scrambled mode.
When operating in Serial TelecomBus mode, the TSEC converts the 8-bit data parallel input
data and the associated control bit to the 8B/10B Serial TelecomBus 10-bit parallel data format.
Code Group
Name
Multiplex Section Termination (MST) Level
K28.5
K28.4
High Order Path Termination (HPT) Mode
K28.5
K28.4
K28.0-
K28.0+
K28.6
Curr. RD-
abcdei fghj
001111 1010
001111 0010
001111 1010
001111 0010
001111 0100
—
001111 0110
Curr. RD+
abcdei fghj
110000 0101
—
110000 0101
—
—
110000 1011
110000 1001
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Encoded Signals
Description
J0 = ‘b1
PL= ‘b0
J0 frame and multiframe alignment
High-order path AIS
J0=’b1
PL=’b0
J0 frame and multiframe alignment
High-order path AIS
PL=’b0
High-order path H3 byte position, no
negative justification event.
PL=’b0
High-order path PSO byte position,
positive justification event.
J1=’b1,
PL=’b1
High-order path frame alignment (J1).
Released
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