PM5364 pmc-sierra, PM5364 Datasheet - Page 244

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
OVR - This bit indicates if a previous transfer has not been acknowledged (an indirect read has
not occurred)
PEND - This bit indicates is asserted when the LCLK is triggered and is cleared when it is read.
The other register bits such as the ESEV, PJEV, NJEV, PJE[12:0], NJE[12:0] in the VTPA are
not affected by this. In addition, the TRIB_INT[x][y][z] bits are functioning proper. This
means when the ESEE bit is set to 1, the TRIB_INT[x][y][z] will indicate a ESE interrupt status
reliably.
To address this issue, a hardware workaround and a software workaround are available.
Hardware:
The VTPA interrupt bit will only be unreliable when the LCLK is triggered at the moment when
the VTPA is processing the fixed stuff byte right below the TU3 H3 byte. The hardware
workaround is to control the assertion time of the LCLK pin to avoid this byte. Since the AU4
H1/H2 pointer is fixed to 522 or 0, the TU3 pointer as well as the sensitive byte will be in a
known location in reference with the system-side frame pulse (EJ0).
Internally generated one-second performance monitor clock and software controllable
performance monitor clock can not be used in this situation.
If the LCLK can be controlled to avoid this sensitive byte, the VTPA interrupt bit will be
asserted reliably. However, in some cases, two reads are needed for clearing the affected bits.
The following formula can be used to determine the timing window that the LCLK assertion
should be avoided.
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•
Note that the numerical values in the above equations represent 77.76 MHz REFCLK clock
cycles. For example, assume PP_FRM_ALIGN_DLY[15:0] = 0, and AU4 pointer = 522. Using
a plus/minus half of the SONET/SDH row as the window size, ie. window size = +/- (45*12) =
+/- 540. Therefore, the timing windows that LCLK should be avoided is from EJ0 +3240-540
to EJ0+3240+540, or from EJ0 + 34.72 ms to EJ0 + 48.61 ms.
Software:
To address this issue in software, the following alternate indications can be used to replace the
function of the affected interrupt bits.
If the AU4 pointer is set at 522, the sensitive byte is located on row 4.
LCLK assertion window to avoid
(3*90*12) + window size
If the AU4 pointer is set at 0, the sensitive byte is located on row 7.
LCLK assertion window to avoid = EJ0 + PP_FRM_ALIGN_DLY[15:0] + 6480
(6*90*12) + window size
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
= EJ0 + PP_FRM_ALIGN_DLY[15:0] + 3240
Released
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