PM5364 pmc-sierra, PM5364 Datasheet - Page 204

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

13.8.7
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
Table 37 Wideband Fabric Switch System Configuration
MSU-Lite Operation
Correct operation of the MSU-Lite requires that the entire time switch control ram be
configured. Switching between the two pages of Switch Control RAM is controlled through the
CMP input. CMP is only sampled during the C1 byte position of the input frame. A page swap
occurs on the first byte of the next frame. The SWAP_PENDINGV bit in the MSU
Configuration register reflects the state of the page swap circuitry. When SWAP_PENDINGV is
logic 1, a change to CMP has been recognized but the page swap has not yet occurred. When in
this state, the Switch Control Ram should not be written to. A change of state of
SWAP_PENDINGV can be configured to generate an interrupt by setting the
SWAP_PENDINGE bit. Reading the Interrupt Status and Memory Page Update register clears
the interrupt.
The MSU provides a mechanism for the on-line page to be copied to the off-line page. To
initiate a page copy, the Interrupt Status and Memory Page Update register must be written to. A
page copy will take approximately 15us to complete. Page copies may also be done
automatically whenever the two pages are swapped. To enable this automated update, the
AUTO_UPDATE bit of the MSU Configuration register must be set to logic 1. During a page
copy, reads or writes of the time switch ram are not permitted. The UPDATEV bit contains the
current status of the page copy circuit and can be used to determine when it is okay to access the
time switch ram. The UPDATEI bit is set on a change of state from high to low of the
UPDATEV status, indicating that the update is finished and it is once again okay to update the
time switch ram. An interrupt can be configured to occur whenever the UPDATEV bit changes
state from high to low by setting the UPDATEE bit to a logic 1. This can be used to indicate to
the microprocessor that a page update has finished. Reading the Interrupt Status and Memory
Page Update register clears the interrupt. The UPDATEI bit is cleared when the Interrupt Status
and Memory Page Update register is read.
Application
Hairpin
Hairpin
Hairpin
ADM
ADM
ADM
ADM
External NSE ADM
External NSE ADM
External NSE ADM
External NSE ADM
Block
Ingress MSUs
CCB
Egress MSU
Ingress MSU
CCB
Egress MSU
External SBS
MSUs
Ingress MSU
CCB
Egress MSU
External NSE
CMP Source
SICMP pin, or top level register
SICMP pin, or top level register.
SECMP pin or top level register
SICMP pin, or top level register
SICMP pin, or top level register
SECMP pin, or top level register
CMP pins, top level registers in SBS or via TILC
overhead OPage bits
SICMP pin, top level register or inband via the TILC
OPage bits
No switching in CCB - bypassed in this setup and is only
used to create reference pulses
SECMP pin, top level register or inband via the TILC
OPage bits
CMP pin or top level pin. NSE can pass Page change
info to TUPP 2488 via RILCs.
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Released
204