PM5364 pmc-sierra, PM5364 Datasheet - Page 231

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

13.13.6
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
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Note
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Interrupt Registers
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RILC CPU Operations
Accessing the Receive Message FIFO
When reading messages from the receive FIFO in the RILC, the following procedure should be
followed:
1. Write a logic 1 to the RX_XFER_SYNC bit of the Receive Status and FIFO Synch Register.
2. Read the RX_FI_BUSY bit in the Receive Status and FIFO Synch Register or wait a
3. Read the Receive Status and FIFO Synch Register and check the state of the CRC_ERR. If
4. Read the Receive FIFO Data High and Receive FIFO Data Low Registers.
5. Read the RX_FI_BUSY bit in the ILC Receive Status and FIFO Synch Register or wait a
6. Loop back to Step 4 until the entire message has been read out of the FIFO.
When reading more than one message from the receive FIFO, the RX_XFER_SYNC does not
have to be set between each message.
A Receive Status Register (RO) that returns status from the message receive logic indicating
number of messages received and stored in the Receive FIFO and the receive FIFO busy
status. Also contained in this register is the status of the received header bits, LINK, PAGE
and USER.
A Receive Auxiliary Register (RO) is used o return the status of the received AUX bits.
A Receive FIFO Synch Register (WO) that aligns the read message pointers to the start of a
message and facilitates the use of short messages and skipping of message buffers.
The Receive Status Register and Receive FIFO Synch Register share the same address.
An Interrupt Enable and Control Register is used to enable interrupts for different events
and configure interrupt variables such as thresholds and timeouts.
An Interrupt Reason Register indicates status of each of the interrupt events. The status of
these bits is updated irrespective of whether the corresponding interrupt enable is set or
clear.
This will initiate a read from the receive FIFO.
minimum of 4 SYSCLK cycles. If RX_FI_BUSY is a logic 0, continue to step 3. If it is a
logic 1, continue polling the RX_FI_BUSY bit.
this bit is a logic 1, the current message in the FIFO had a CRC error and the data is not
reliable and the user may want to skip to the next message.
minimum of 4 SYSCLK cycles. If RX_FI_BUSY is a logic 0, continue to step 6. If it is a
logic 1, continue polling the RX_FI_BUSY bit.
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Released
231