PM5364 pmc-sierra, PM5364 Datasheet - Page 87

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

10.2.5
10.2.6
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
The ALIGN_FIFO decouples phase, jitter, and wander between the 77 MHz core clock and the
recovered clock from the SERDES block. The depth of the ALIGN_FIFO allows for interlink
skew between the links of an interface, for example, the eight working and protect line side
links.
The ALIGN_FIFO is 36 words deep (36x9bit) with write side logic ensuring J0 data appears at
address 0. The read pointer will naturally wrap around to the J0 byte location as the FIF0 size
divides evenly into the STS-12/STM-4 frame size. The ALIGN_FIFO processes only STS-
12/STM-4 equivalent flows from the RSEF slice.
The STS-12 signal generated by the ALIGN_FIFO is aligned to a programmable offset
(LINE_INGRESS_REF_DLY) from the device frame start marker input IJ0. The offset frame
start marker is referred to as RXJ0FP. The alignment distance between the receive frame pulse
J0 marker generated by RSEF (indicates when the J0 character is written into address zero of
the FIFO) and RXJ0FP is measured and can be read out with the DISTANCE bits in the CML
Rx Slice Distance register. The offset is programmed such that the DISTANCE bits report a
FIFO depth that is acceptable for accommodating receive clock jitter and the skew between
serial streams from the different links of an interface.
expected time (coincident with RXJ0FP). The alignment failure is recorded in the CML Rx
Slice INT_STATUS register. Optionally an interrupt is generated, enabled by the CML Rx Slice
INT_ENABLE register.
An ALIGN_FIFO error is indicated and an interrupt is optionally generated whenever the read
and write pointers are within 1 FIFO location of each other. The pointers continuously
increment and are frequency locked so they are only compared when the write pointer wraps
back to the first location in the FIFO.
TelecomBus Decoder (TCB Decoder)
A TCB Decoder block is required whenever the RSEF block is connected to the internal byte-
wide 77.76 MHz TelecomBus. The TCB Decoder block decodes the 9-bit bus from RSEF
(K + 8 bits data) into the byte-wide TelecomBus signals required by downstream blocks in the
device.
Receive Inband Link Controllers (RILC)
The RILC block is used only on the system side of TUPP 2488 for the eight working and eight
protect System Egress and System Ingress Serial RASIO™ CML links. The RILC block is used
in the System Egress path.
Loss of alignment is declared when the J0 pulse is not available in the ALIGN_FIFO at the
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Released
87