PM5364 pmc-sierra, PM5364 Datasheet - Page 239

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
Figure 63 Boundary Scan Architecture
The boundary scan architecture consists of a TAP controller, an instruction register with
instruction decode, a bypass register, a device identification register and a boundary scan
register. The TAP controller interprets the TMS input and generates control signals to load the
instruction and data registers. The instruction register with instruction decode block is used to
select the test to be executed and/or the register to be accessed. The bypass register offers a
single-bit delay from primary input, TDI to primary output, TDO. The device identification
register contains the device identification code.
The boundary scan register allows testing of board inter-connectivity. The boundary scan
register consists of a shift register place in series with device inputs and outputs. Using the
boundary scan register, all digital inputs can be sampled and shifted out on primary output,
TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital
outputs.
TRSTB
TMS
TCK
TDI
Controller
Access
Test
Port
Device Identification
Control
Tri-state Enable
Select
Boundary Scan
Instruction
Register
Register
Register
Register
Decode
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Bypass
and
Mux
DFF
Released
239
TDO