PM5364 pmc-sierra, PM5364 Datasheet - Page 67

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
Pin Name
LREFCLK_P
LREFCLK_N
Reserved
Reserved
Reserved
SREFCLK_P
SREFCLK_N
Reserved
Reserved
Reserved
Analog Miscellaneous Signals (System Side) (10 pins)
Type
2.5 V
LV-PECL
externally
AC-
coupled
input
Analog
Output
Analog I/O
Analog I/O
2.5 V
LV-PECL
externally
AC-
coupled
input
Analog
Output
Analog I/O
Analog I/O
Pin No.
A27
B27
A24
B24
D25
C25
D26
C26
B26
A26
AP9
AN9
AK12
AL12
AN11
AM11
AP10
AN10
AM10
AL10
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Function
Line Side Analog Reference Clock. These
differential signals provide a reference clock for the
clock synthesis unit on the line side of TUPP 2488.
LREFCLK_P/N must be a 155.52 MHz clock, with a
nominal 50% duty cycle.
The reference frequency differential input signal
should be derived from an external source. The
signals are AC-coupled to a RASIO™ CML
Receiver before being used by the CSU.
The reference frequencies are expected to be
PECL level signals for better jitter performance of
the system.
LREFCLK_P/N and SREFCLK_P/N must be
frequency locked to the digital reference clock chip
input REFCLK
These pins are reserved and should be left floating.
These pins are reserved and should be left floating.
These pins are reserved and should be left floating.
System Side Analog Reference Clock. These
differential signals provide a reference clock for the
clock synthesis unit on the line side of TUPP 2488.
SREFCLK_P/N must be a 155.52 MHz clock, with
a nominal 50% duty cycle.
The reference frequency differential input signal
should be derived from an external source. The
signals are AC-coupled to a RASIO™ CML
Receiver before being used by the CSU.
The reference frequencies are expected to be
PECL level signals for better jitter performance of
the system.
LREFCLK_P/N and SREFCLK_P/N must be
frequency locked to the digital reference clock chip
input REFCLK
These pins are reserved and should be left
floating.
These pins are reserved and should be left floating.
These pins are reserved and should be left floating.
Released
67