PM5364 pmc-sierra, PM5364 Datasheet - Page 199

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

13.8.4
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
When sending CMP changes via TILC to external devices, care needs to be taken when
changing the CMP value. An interrupt is made available to the TUPP 2488 CPU called the
Frame Interrupt. This occurs when CMP would normally be sampled (at the EJ0 frame
flywheeled pulse). This interrupt is maskable and would normally be masked.
The CPU will need to enable this interrupt before a page switch is required, then respond to this
interrupt immediately and complete writing the new page bit settings within 27 µs.
This is required since the TILC will sample the page bits once during the frame before the first
message is assembled and sent (starting at the beginning of row 3). If the page bits are updated
late, the Slave switches’ (MSUs) pages will switch a frame later than those of the Master switch
(crossbar) causing 1 frame of data corruption.
The Master’s CPU will have the rest of the frame to signal a page switch to the Crossbar as this
is sampled on the next frame.
Figure 42 Page Switching Via ILC
CPU Interaction With the Switching Cycle When Using the ILC
EJ0 frame flywheeled
Framei interrupt
Master CPU
Crossbar J0
Crossbar sample
Enable Frame
MSU sample
tasks
Interrupt
new bit
new bit
Write new MSU
page words
Crossbar samples CMP
bit and set up page switch
message
outgoing
Write new Crossbar
disable Frame
page bit and
interrupt
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
MSU samples new page
bits and set up page
switch
messages
outgoing
Switch occurs in the
Crossbar
Switch occurs in the MSU
Released
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