PM5364 pmc-sierra, PM5364 Datasheet - Page 280

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
Table 61 Microprocessor Interface Write Access
Symbol
tSAW
tSDW
tSALW
tHALW
tVL
tSLW
tHLW
tHDW
tHAW
tVWR
Figure 90 Microprocessor Interface Write Timing
Notes
1.
2.
3.
(CSB+WRB)
A valid write cycle is defined as a logical OR of the CSB and the WRB signals
In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALW,
tHALW, tVL, and tSLW are not applicable
Parameter tHAW is not applicable if address latching is used
D[15:0
]
A[14:0
]
ALE
Parameter
Address to Valid Write Set-up Time
Data to Valid Write Set-up Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
Latch to Write Set-up
Latch to Write Hold
Data to Valid Write Hold Time
Address to Valid Write Hold Time
Valid Write Pulse Width
tS AL
tV L
tS AW
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
tS LW
Valid Address
10
20
10
10
20
0
5
5
40
Min
5
tS
tV
Valid Data
WR
DW
tH AL
Max
—
—
—
—
—
—
—
—
—
—
tH
tH LW
DW
tH AW
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Released
280