PM5364 pmc-sierra, PM5364 Datasheet - Page 77

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
The line side RASIO™ CML links of TUPP 2488 can operate at a different rate than the system
side RASIO™ CML links. For example, the line side RASIO™ CML links can operate at 2.488
Gbit/s while the system side RASIO™ CML links of TUPP 2488 can operate at 777.6 Mbit/s.
For a 2.488 Gbit/s (or 622.08 Mbit/s) RASIO™ CML interface, the VCO inside the
RA013_CSUSLICE needs generates a clock frequency of 2.488 GHz. For a 777.6 Mbit/s
RASIO™ CML interface, the VCO inside the RA013_CSUSLICE generates a clock frequency
of 3.111 GHz. Therefore, two separate RA013_CSUSLICE blocks are required in the TUPP
2488.
There are two RA013_SERDES blocks in TUPP 2488 — one on the line side and one on the
system side. On the line side, the RA013_SERDES block contains four RA013_RXSLICE
blocks, four RA013_TXCSLICE blocks, and one RA013_CSUSLICE block. On the system
side, the RA013_SERDES block contains eight RA013_RXSLICE blocks, eight
RA013_TXCSLICE blocks, and one RA013_CSUSLICE block. Therefore, in total there are 12
RA013_RXSLICE blocks, 12 RA013_TXCSLICE blocks, and two RA013_CSUSLICE blocks
in the TUPP 2488 device.
The RA013_RXSLICE block consists of two RX_3330 blocks and two RA013_DCRU blocks
to provide complete receiver side functionality for two links (i.e. working and protect).
The RA013_TXCSLICE block consists of two TX_3330 blocks and two PISO_3330 blocks to
provide complete transmitter side functionality for two links (i.e. working and protect).
The RA013_CSUSLICE consists of the RA013_CSU block and the CLKPHASEGEN block.
The CSUI (CSU Interface) functional block provides a convenient interface to the
RA013_CSUSLICE functions. The CSUI monitors clock synchronization between the
RA013_CSUSLICE PLL divided clock and the system reference clock. The CSUI always
shows that the two clocks are locked if the clocks differ by no more than 244 PPM. The CSUI
always shows that the two clocks are not locked if the clocks differ by more than 1220 PPM.
Any change in lock status causes the CSUI to generate a maskable interrupt.
Receive Buffer (RX_3330)
The RX_3330 block is a 3.33 Gbit/s RASIO™ CML/ELVDS receiver. Complete RASIO™
CML multi-rate configurable serial links operating at speeds up to 3.33 Gbit/s can be realized
when the RX_3330 is combined with the TXCML_3330.
RX_3330 is a sensitive comparator and buffer that interfaces directly with the media and
restores the amplitude of the degraded data. The RX_3330 presents a 100Ω differential
termination (internally terminated) impedance to terminate the lines.
Data and Clock Recovery (RA013_DCRU)
RA013_DCRU takes in the restored amplified data from RX_3330 and recovers the phase and
hence the clock and data. RA013_DCRU also deserializes the high-speed serial data to 8-bit or
10-bit low-speed parallel data and outputs it with a synchronized low speed clock.
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Released
77