PM5364 pmc-sierra, PM5364 Datasheet - Page 21

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

2.2
2.2.1
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
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Payload Processing Features
The payload-processing blocks are provided in the ingress path of TUPP 2488 and perform
payload processing on traffic from the line ingress path before it is output on either the system
ingress (via the switch matrix) or line egress paths.
General Payload-Processing Features
The following features are available to both VT/TU mapped traffic and also bypass traffic.
Bypass traffic consists of non VT-TU mapped payloads i.e. STS-1, AU3/VC3/C3,
AU4/VC4/C4, and contiguous concatenated payloads STS-3c, STS-12c/AU4-4c,
STS-48c/AU4-16c.
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In ADM applications, provides maximum steady-state latency of 38.73 µs from line ingress
to system ingress for VT1.5 and maximum steady state latency of 22.56 µs from system
egress to line egress for VT1.5. In pure payload processing applications provides maximum
steady state latency of 19.69 µs from line ingress to line egress for VT1.5. In hair-pinning
applications provides maximum steady state latency of 56.9 µs from line ingress to line
egress for VT1.5.
Supports contiguously concatenated payloads (STS-3c, STS-12c/AU-4-4c, STS-48c/AU-4-
16c).
Provides the ability to overwrite a line side transport overhead byte prior to egress.
On egress path, provides optional SDH payload conversions as follows:
o 3x AU3/VC3/C3 to AU4/VC4/TUG3/TU3/VC3/C3
o 3x AU3/VC3/TUG2 to AU4/VC4/TUG3/TUG2
Provides a generic 16-bit microprocessor bus interface for configuration, control, and status
monitoring.
Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan test purposes.
Implemented in 1.2 V core and 2.5 V I/O 0.13
tolerant. The MPIF data bus, Egress Parallel TelecomBus, and REFCLK input are
programmable to 2.5 V or 3.3 V. REFCLK and the Egress Parallel TelecomBus voltage are
programmed from the same source.
580-ball CSBGA+ package.
Aligns the synchronous payloads of a SONET/SDH STS-48/STM-16 or four
STS-12/STM-4 byte serial streams to a new transport frame reference (J0).
Inserts valid high order pointer bytes (H1, H2), framing bytes (A1, A2).
Allows the following SDH payload conversions:
o 3x AU3/VC3/C3 to AU4/VC4/TUG3/TU3/VC3/C3
o 3x AU3/VC3/TUG2 to AU4/VC4/TUG3/TUG2
Note: Mixing AU3/VC3/C3 and AU3/VC3/TUG2 payloads in an AU4 during AU3 to AU4
conversion is not supported.
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
µ
m CMOS technology. Inputs are 3.3 V
Released
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