PM5364 pmc-sierra, PM5364 Datasheet - Page 52

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
Pin Name
TPOHFP[4]
TPOHFP[3]
TPOHFP[2]
TPOHFP[1]
TRAD[4]
TRAD[3]
TRAD[2]
TRAD[1]
HPOHFP
HPOHCLK
High Order Path Overhead and Alarm Interface (17 pins)
Type
Output
Output
Output
Output
Pin No.
U3
T1
P4
N4
U2
R4
P3
N3
M4
N2
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Function
Tributary Path Overhead Frame Pulse. The
tributary path overhead frame pulse (TPOHFP[4:1])
signals may be used to locate the individual path
overhead bits of each tributary for the
corresponding STS-12/STM-4 stream. Each
TPOHFP signal is set high to mark bit 1 (the most
significant bit) of the V5 byte of the first tributary.
TPOHFP[4:1] is updated on the rising edge of
REFCLK.
Tributary Remote Alarm Port. The remote alarm
port (TRAD[4:1]) contains the tributary path BIP
error count, the RDI status and the PDI status of
each tributary in the corresponding STS-12/STM-4
when the TRAD_BIPE_SEL register is ‘0’. In this
case the BIP-8 count for TU3s is output over 4
timeslots.
When TRAD_BIPE_SEL is ‘1’ the BIP-8 count for
TU3s is output in one timeslot.
Refer to Section 14.6 for a detailed description of
the TRAD port.
TRAD[4:1] is updated on the rising edge of
REFCLK.
High Order Path Overhead Frame Pulse. The
high order path overhead frame pulse signal
provides frame reference timing for serial path
overhead extraction and insertion streams.
HPOHFP is used to indicate the most significant bit
(MSB) of the J1 byte on HRPOH[4:1] and the first
possible path BIP error on HB3E[4:1].
HPOHFP can be sampled on the rising edge of
HPOHCLK.
HPOHFP is updated on the falling edge of
HPOHCLK.
High Order Path Overhead Clock. The high order
path overhead clock signal provides timing for the
serial path overhead extraction and insertion
streams.
This clock is a nominal 20.736 MHz clock
generated by dividing down and gapping the
77.76 MHz reference clock (REFCLK). HPOHCLK
has a 33% high duty cycle.
Released
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