PM5364 pmc-sierra, PM5364 Datasheet - Page 94

• Manufacturer Part Number: PM5364
• Description: Tupp 2488 Assp Telecom Standard
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2011334, Issue 7
When the Line Ingress interface selected is Ingress Byte-Wide TelecomBus, only one of the
STSI blocks in the Line Ingress path is used. When the Line Ingress format selected is Serial
CML, both STSI blocks in the Line Ingress path are used. Similarly, only one of the STSI
blocks in the Line Egress path is used when the Line Egress interface selected is Byte-Wide
TelecomBus.
The STSI blocks can form the “Time” stage of a Time:Space:Time switch fabric in conjunction
with external TSE and TBS devices. The STSI blocks effectively function as a TBS device.
The STSI is used to reorder the timeslots inside a SONET/SDH data stream. The timeslots can
be reordered at an STS-1/STM-0 granularity. Any STS-1/STM-0 can be dropped, moved or
copied to one or more STS-1/STM-0 data streams inside a SONET/SDH data stream.
The STSI reorders the timeslots of four STS-12/STM-4 parallel format data streams. The four
data streams are required to be aligned on the same transport frame. This permits the STSI to
reorder the timeslots both within and across the four SONET/SDH data streams.
The STSI uses two connection memory pages. Either of the two pages specifies the re-ordering
operations to be performed on the data streams. In normal operation, one of the pages is active,
containing the information used to reorder the current data stream. The other page can be
updated by an external microprocessor in the background. When a connection memory change
is indicated, the two pages are swapped and the most recently updated page becomes the active
page. Page selection is done using the LICMP pin on the line ingress interface and the LECMP
pin on the line egress interface or using top-level registers. The change of page selection is
aligned to the second next transport frame boundary to provide hitless switchover.
The LICMP pin is sampled on the IJ0 reference pulse when using the Line serial bus. A
programmable delay value in top-level registers specifies when the ingress STSI blocks expect
to see a J0 in relation to the IJ0 reference pulse. Glue logic is used to wait for this
programmable delay before updating the CMP input to the ingress STSI blocks. Similarly, the
LECMP pin is sampled on the IJ0 reference pulse, and a programmable delay is used before
updating the CMP input to the egress STSI blocks.
When using Parallel bus, CMPs are sampled on IJ0J1 and EJ0J1for the Ingress and Egress
STSIs respectively.
The re-ordering of the input STS-1/STM-0 payload is based on the output STS-1/STM-0
payload. Each output STS-1/STM-0 time slot is associated with one input STS-1/STM-0 time
slot.
The STSI can be set in a bypass mode by programming passthru switch settings. The STSI can
also operate in an OC-48c to OC-12 translation mode, or OC-12 to OC-48c translation mode. In
the translation modes, the connection memory pages are not used.
The LIWTSEN outputs on the working STSI block in the line ingress interface can be used to
control multiplexers which select combinations of STS-1’s from both working and protect Line
Ingress Serial RASIO™ CML links. Changes to the selection of working and protect links are
synchronized to the frame boundary to provide hitless switchover.
TUPP™ 2488 ASSP Telecom Standard Product Data Sheet
Released
94