XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 104

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-II Pro
source-synchronous transmitter and receiver data-valid windows.
Table 55: Duty Cycle Distortion and Clock-Tree Skew
DS083-3 (v2.12) November 11, 2003
Advance Product Specification
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For
2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew
Duty Cycle Distortion
Clock Tree Skew
cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by
asymmetrical rise/fall times.
T
T
in the I/O.
exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
DCD_CLK0
DCD_CLK180
Description
R
applies to cases where local (IOB) inversion is used to provide the negative-edge clock to the DDR element in the I/O.
(2)
applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element
(1)
T
T
DCD_CLK180
T
Symbol
DCD_CLK0
CKSKEW
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
1-800-255-7778
XC2VP100
XC2VP125
XC2VP100
XC2VP125
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
XC2VP2
XC2VP4
XC2VP7
Device
All
–
7
Speed Grade
0.13
0.21
0.22
0.30
0.41
0.59
–
6
0.13
0.22
0.24
0.32
0.42
0.64
–
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
47