XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 108

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

DS083-3 (v2.12) November 11, 2003
Advance Product Specification
11/20/02
11/25/02
12/03/02
01/20/03
03/24/03
Date
R
Version
2.3
2.4
2.5
2.6
2.7
Updated parametric information in:
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Table
Updated parametric information in:
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Updated parametric information in:
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Table
3.75V. Delete cautionary footnotes related to voltage overshoot/undershoot.
Table
referencing special information for 3.3V operation. Add footnote for PCI/PCI-X.
Table
Table
Table
Correct max V
Table
Table
Table
Output Voltage Swing.
Table
Table
Table
Table
(except PCI/PCI-X) to 0 pF.
Table
Table
3.3V.
Table
Table
(single-ended) and DV
Table
REFCLK2, BREFCLK, and BREFCLK2; correct T
measurement.
Table
Table
Table
Add footnote (2) to qualify Max T
Table
Move clock parameters from
Added/updated timing parameters from speedsfile v1.76.
Table
Table
Table
Table
Table
Table
Table
Table
Table
1: Correct lower limit of voltage range of V
1: Increase Absolute Max Rating for V
2: Delete V
3: Add I
4: Add Typical Quiescent Supply Currents for XC2VP4 and XC2VP7 only
6: Correct I
7: Correct Min/Max V
10: Reformat LVPECL DC Specifications to match Virtex-II data sheet format
11: Correct parameter name from Differential Output Voltage to Single-Ended
15: Add CPMC405CLOCK max frequencies
23: Add footnote regarding serial data rate limitation in -5 part.
31: Add rows for LVTTL, LVCMOS33, and PCI-X.
32: Add LVTTL, LVCMOS33, and PCI-X. Correct all capacitive load values
42: Correct CCLK max frequencies
1: Correct lower limit of voltage range of V
2: Add footnote (2) regarding V
11: Add waveform diagrams
21: Indicate REFCLK upper frequency limitation; relate REFCLK parameters to
51: Add qualifying footnote to CLKOUT_DUTY_CYCLE_DLL
11: Correct DV
21: Correct T
50: Correct hyperlink in footnote (1) to point directly to Answer Record 13645.
2: Delete first table footnote and renumber all others.
3: Add "sample-tested" to I
8: Update V
10: Update LVPECL_25 DC parameters.
21: Update F
23: Update F
31: Update V
34,
55: Break out T
Table
BATT
IH
35: Correct parameter name "CE input (WS)" to "SR input".
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
from V
OL
CCO
OCM
. Delete I
www.xilinx.com
1-800-255-7778
GCLK
GTX
RCLK
REF
and I
IN
DCD_CLK0
specifications for 2.5V and below operation. Delete footnote
PPOUT
(Typ) to 1.250V.
Min (200 mV to 175 mV) and DV
frequency ranges. Correct T
(Typ) for HSTL Class I/II from 1.08V to 0.90V.
CCO
/T
frequency ranges. Break out T
OH
FCLK
L
OD
[Table 32
for SSTL2 I. Add rows for LVTTL, LVCMOS33, and PCI-X.
to 3.6V.
specifications for 2.5V and below operation.
Table
(differential).
, V
by device type.
Typ (400 ps to 600 ps) and Max (600 ps to 1000 ps).
OCM
GJTT
L
. Remove "Device" column, unnecessary.
(Figure 1
17,
Revision
, and V
CCAUX
removed in v2.8.]
parameter.
Table
ICM
IN
voltage droop. Renumbered other notes.
CCO
and
18,
and V
IN
, V
Table
Figure
RCLK
and V
REF
DJ
TS
, V
to 0.17 UI, T
19, and
and T
GJTT
from –0.3V to –0.5V for 3.3V.
IN
2) illustrating DV
TS
IN
Max (1000 mV to 2000 mV).
, and V
from –0.5V to –0.3V for
by operating speed.
FCLK
Table 20
TS
values and unit of
.
RJ
from 3.6V to
to o.18 UI.
to
OUT
Table
15.
51