XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 50

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

where M and D are two integers. Specifications for M and D
are provided under DCM Timing Parameters in
Sheet Module
in a clock output frequency four times faster than the clock
input frequency (CLKIN).
CLK2X180 is phase shifted 180 degrees relative to CLK2X.
CLKFX180 is phase shifted 180 degrees relative to CLKFX.
All frequency synthesis outputs automatically have 50/50
duty cycles, with the exception of the CLKDV output when
performing a non-integer divide in high-frequency mode.
See
Note that CLK2X and CLK2X180 are not available in
high-frequency mode.
Table 23: CLKDV Duty Cycle for Non-integer Divides
Two separate components of the phase shift range must be
understood:
•
•
The
equation:
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
PHASE_SHIFT
FINE_SHIFT_RANGE
PHASE_SHIFT
Table 23
CLKDV_DIVIDE
R
CLKOUT_PHASE_SHIFT
= NONE
CLKOUT_PHASE_SHIFT
= FIXED
CLKOUT_PHASE_SHIFT
= VARIABLE
for more details.
1.5
2.5
3.5
4.5
5.5
6.5
7.5
3. By default, M = 4 and D = 1, which results
attribute range
attribute is the numerator in the following
DCM timing parameter range
CLKIN
CLKFB
CLKIN
CLKFB
CLKIN
CLKFB
Duty Cycle
Figure 54: Fine-Phase Shifting Effects
5 / 11
6 / 13
7 / 15
3 / 7
2 / 5
4 / 9
1/ 3
(PS/256) x PERIOD CLKIN
(PS negative)
(PS/256) x PERIOD CLKIN
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1-800-255-7778
Data
(PS negative)
Phase Shifting
The DCM provides additional control over clock skew
through either coarse or fine-grained phase shifting. The
CLK0, CLK90, CLK180, and CLK270 outputs are each
phase shifted by ¼ of the input clock period relative to each
other, providing coarse phase control. Note that CLK90 and
CLK270 are not available in high-frequency mode.
Fine-phase adjustment affects all nine DCM output clocks.
When activated, the phase shift between the rising edges of
CLKIN and CLKFB is a specified fraction of the input clock
period.
In variable mode, the
dynamically incremented or decremented as determined by
PSINCDEC synchronously to PSCLK, when the PSEN
input is active.
shifting. For more information on DCM features, see the
Virtex-II Pro Platform FPGA User Guide.
Table 24
variable mode.
Table 24: Fine Phase Shifting Control Pins
The full range of this attribute is always -255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the
the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
Virtex-II Pro™ Platform FPGAs: Functional Description
PSINCDEC
PSEN
PSCLK
PSDONE
Control Pin
Phase Shift (ns) = (
FINE_SHIFT_RANGE
lists fine-phase shifting control pins, when used in
(PS/256) x PERIOD CLKIN
(PS positive)
(PS/256) x PERIOD CLKIN
Figure 54
Direction
(PS positive)
Out
In
In
In
PHASE_SHIFT
PHASE_SHIFT
illustrates the effects of fine-phase
component, which represents
Increment or decrement
Enable ± phase shift
Clock for phase shift
Active when completed
/256) * PERIOD
DS031_48_110300
value can also be
Function
CLKIN
41