XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 92

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Configuration Timing
Configuration Memory Clearing Parameters
Power-up timing of configuration signals is shown in
Table 40: Power-Up Timing Characteristics
DS083-3 (v2.12) November 11, 2003
Advance Product Specification
Notes:
1. The M2, M1, and M0 mode pins should be set at a constant DC voltage level, either through pullup or pulldown resistors, or tied
directly to ground or V
Program Pulse Width
CCLK (output) Delay
R
Program Latency
Power-on-Reset
Description
CCAUX
PROG_B
INIT_B
Vcc
. The mode pins should not be toggled during and after configuration.
Figure 7: Power-Up Timing Configuration Signals
*Can be either 0 or 1, but must not toggle during and after configuration.
T
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
Figure
Symbol
CCLK OUTPUT or INPUT
PROGRAM
www.xilinx.com
1-800-255-7778
T
T
T
T
ICCK
POR
POR
PL
7; corresponding timing characteristics are listed in
M0, M1, M2*
(Required)
T
PL
T
Value
PL
300
T
4
ICCK
+ 2
ds083-3_07_091003
µ
s per frame, max
ms, max
µ
ns, min
µ
Units
s, max
s, min
Table
40.
35