XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 85

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Virtex-II Pro Switching Characteristics
I/O
Input Delay Measurements
Table 31
ing Input standard adjustments (see
Table 31: Input Delay Measurement Methodology
28
Notes:
1.
2.
3.
4.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI-X
GTL
GTLP
HSTL Class I
HSTL Class II
HSTL Class III
HSTL Class IV
HSTL18
Class I
HSTL18
Class II
HSTL18
Class III
HSTL18
Class IV
SSTL2
Class I & II
SSTL18
Class I & II
LVDS25
LVDSEXT25
ULVDS25
LDT25
Standard
Standard Adjustment Measurement Methodology
Input waveform switches between V
Measurements are made at typical, minimum, and maximum V
values. Reported delays reflect worst case of these measurements.
V
User Guide
Input voltage level from which measurement starts.
Note that this is an input voltage reference that bears no relation to
the V
Figure
REF
REF
values listed are typical. See
shows the test setup parameters used for measur-
6.
/ V
MEAS
for min/max specifications.
V
1.2 – 0.125
1.2 – 0.125
0.6 – 0.125
0.6 – 0.125
V
V
V
V
V
V
V
V
V
V
V
REF
parameters found in IBIS models and/or noted in
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
V
L
0
0
0
0
0
– 0.75
(1)
Per PCI-X Specification
– 0.2
– 0.2
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
Per PCI Specification
Per PCI Specification
V
1.2 + 0.125
1.2 + 0.125
0.6 + 0.125
0.6 + 0.125
V
V
V
V
V
V
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Virtex-II Pro Platform FPGA
L
V
and V
3.3
3.3
2.5
1.8
1.5
H
+ 0.75
(1)
+ 0.2
+ 0.2
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
Table 28, page
H
.
V
V
V
V
V
V
V
V
V
V
V
V
V
1.65
1.25
0.75
1.65
MEAS
(3,4)
0.9
1.2
1.2
0.6
0.6
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
22).
V
0.80
0.75
0.75
0.90
0.90
0.90
0.90
1.08
1.08
1.25
(2,4)
1.0
0.9
www.xilinx.com
REF
1-800-255-7778
–
–
–
–
–
–
–
–
REF
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pf) across approximately 4" of FR4
microstrip trace. Standard termination was used for all test-
ing. (See
details.) The propagation delay of the 4" trace is character-
ized separately and subtracted from the final measurement,
and is therefore not included in the generalized test setup
shown in
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it. (IBIS
models can be found on the web at
inx.com/support/sw_ibis.htm.) Parameters V
C
I/O standard. The most accurate prediction of propagation
delay in any given application can be obtained through IBIS
simulation, using the following method:
1. Simulate the output driver of choice into the generalized
2. Record the time to V
3. Simulate the output driver of choice into the actual PCB
4. Record the time to V
5. Compare the results of steps 2 and 4. The increase or
REF
test setup, using values from
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
decrease in delay should be added to or subtracted
from the I/O Output Standard Adjustment value
(Table
delay (clock-to-input) of the PCB trace.
, and V
FPGA Output
Figure
Virtex-II Pro Platform FPGA User Guide
30) to yield the actual worst-case propagation
Figure 6: Generalized Test Setup
MEAS
6.
fully describe the test conditions for each
V
MEAS
MEAS
REF
DS083-3 (v2.12) November 11, 2003
R
C
(probe capacitance)
Advance Product Specification
.
.
REF
REF
V
(voltage level at which
delay measurement is taken)
Table
MEAS
32.
http://support.xil-
ds083-3_06a_092503
REF
, R
REF
for
R
,