XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 8

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XC2VP70

Manufacturer Part Number
XC2VP70
Description
Virtex-ii Pro Field Programmable Gate Array
Manufacturer
Xilinx, Inc.
Datasheet

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Maximum Performance
Maximum RocketIO transceiver and PowerPC processor block performance varies, depending on the package style and
speed grade. See
the FPGA fabric performance parameters.
Table 4: Maximum RocketIO Transceiver and Processor Block Performance
Virtex-II Pro Ordering Information
Virtex-II Pro ordering information is shown in
Revision History
This section records the change history for this module of the data sheet.
DS083-1 (v2.4.2) August 25, 2003
Advance Product Specification
RocketIO Transceiver Wirebond (FG)
RocketIO Transceiver FlipChip (FF)
PowerPC Processor Block
01/31/02
06/13/02
09/03/02
09/27/02
11/20/02
01/20/03
03/24/03
08/25/03
Date
R
Table 4
Version
2.4.1
2.4.2
1.0
2.0
2.1
2.2
2.3
2.4
Example: XC2VP7-7FG456C
Speed Grade
Device Type
(-5, -6, -7)
for details.
Initial Xilinx release.
New Virtex-II Pro family members. New timing parameters per speedsfile v1.62.
Updates to
In
Add bullet items for 3.3V I/O features.
Table
In
Remove FF1517 package option for XC2VP40.
Correct number of single-ended I/O standards from 19 to 22.
Correct minimum RocketIO serial speed from 622 Mbps to 600 Mbps.
Add footnote referring to XAPP659 to callout for 3.3V I/O standards on page 4.
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
Table
Figure 1: Virtex-II Pro Ordering Information
1, correct max number of XC2VP30 I/Os to 644.
Table 1
3, add FG676 package option for XC2VP20, XC2VP30, and XC2VP40.
Figure
3.125
and
400
2.5
-7
1.
www.xilinx.com
1-800-255-7778
Table
Virtex-II Pro™ Platform FPGAs: Introduction and Overview
3. Processor Block information added to
Temperature Range:
Number of Pins
Package Type
C = Commercial (Tj = 0˚C to +85˚C)
I = Industrial (Tj = -40˚C to +100˚C)
Speed Grade
3.125
350
Revision
2.5
-6
DS083_02_052902
300
2.0
2.0
-5
Table
contains the rest of
4.
Units
Gb/s
Gb/s
MHz
7

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