XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 42

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Table 15: Virtex-II Pro Logic Resources Available in All CLBs
18 Kb Block SelectRAM+ Resources
Introduction
Virtex-II Pro devices incorporate large amounts of 18 Kb
block SelectRAM+ resources. These complement the dis-
tributed SelectRAM+ resources that provide shallow RAM
structures implemented in CLBs. Each Virtex-II Pro block
SelectRAM+ resource is an 18 Kb true dual-port RAM with
two independently clocked and independently controlled
synchronous ports that access a common storage area.
Both ports are functionally identical. CLK, EN, WE, and
SSR polarities are defined through configuration.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for write) and Data/parity
data outputs (for read).
Operation is synchronous; the block SelectRAM+ behaves
like a register. Control, address and data inputs must (and
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
Configuration
Virtex-II Pro block SelectRAM+ supports various configura-
tions, including single- and dual-port RAM and various
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
Notes:
1. The carry-chains and SOP chains can be split or cascaded.
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP100
XC2VP125
Device
R
CLB Array:
136 x 106
104 x 82
120 x 94
Column
16 x 22
40 x 22
40 x 34
56 x 46
80 x 46
88 x 58
88 x 70
Row x
Number
13,696
19,392
23,616
33,088
44,096
55,616
Slices
1,408
3,008
4,928
9,280
of
Number
of LUTs
111,232
18,560
27,392
38,784
47,232
66,176
88,192
2,816
6,016
9,856
www.xilinx.com
1-800-255-7778
Max Distributed
SelectRAM+ or
Shift Register
1,058,816
1,411,072
1,779,712
157,696
296,960
438,272
620,544
755,712
45,056
96,256
(bits)
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in
Table 16: Dual- and Single-Port Configurations
Single-Port Configuration
As a single-port RAM, the block SelectRAM+ has access to
the 18 Kb memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kb
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of the 9-bit, 18-bit
and 36-bit widths is the ability to store a parity bit for each
eight bits. Parity bits must be generated or checked exter-
nally in user logic. In such cases, the width is viewed as
8 + 1, 16 + 2, or 32 + 4. These extra parity bits are stored
and behave exactly as the other bits, including the timing
parameters. Video applications can use the 9-bit ratio of
Virtex-II Pro block SelectRAM+ memory to advantage.
Each block SelectRAM+ cell is a fully synchronous memory
as illustrated in
bus widths are identical.
Virtex-II Pro™ Platform FPGAs: Functional Description
16K x 1 bit
8K x 2 bits
4K x 4 bits
Number of
Flip-Flops
111,232
18,560
27,392
38,784
47,232
66,176
88,192
Figure
2,816
6,016
9,856
38. Input data bus and output data
Carry Chains
Number of
116
140
164
188
212
44
44
68
92
92
512 x 36 bits
1K x 18 bits
2K x 9 bits
(1)
Chains
Number
of SOP
Table
112
160
176
176
240
272
208
32
80
80
(1)
16.
33