XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 62

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current
during power-on to insure proper device initialization. The
actual current consumed depends on the power-on ramp
rate of the power supply.
The V
200 µs and no slower than 50 ms. Ramp-on is defined as:
0 V
V
supplies can be turned on in any sequence, though V
must power on before or with V
shown in
Table 5: Power-On Current for Virtex-II Pro Devices
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is essential.
Consult Xilinx Application Note
mation on power distribution system design.
V
this supply voltage is especially susceptible to power supply
noise. V
if V
simultaneously switching output (SSO) limits is essential for
keeping power supply noise to a minimum. Refer to
DS083-3 (v2.12) November 11, 2003
Advance Product Specification
Notes:
1. Power-on current parameter values are specified for Commercial Grade. For Industrial Grade values, multiply Commercial Grade
CCAUX
I
CCAUX
I
CCAUXMIN
Symbol
CCINTMIN
I
CCOMIN
DC
CCO
values by 1.5.
CCINT
to minimum supply voltages (see
CCAUX
and V
powers critical resources in the FPGA. Therefore,
does not have excessive noise. Staying within
Table 5
R
XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 XC2VP125
power supply must ramp on no faster than
CCO
can share a power plane with V
500
250
100
to apply.
can power on at any ramp rate. Power
500
250
100
XAPP623
CCO
500
250
100
for the specifications
Table
for detailed infor-
600
250
100
CCO
2).
, but only
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
CCAUX
www.xilinx.com
1-800-255-7778
800
250
100
Device
Table 5
devices for proper power-on and configuration.
If the current minimums shown in
device powers on properly after all three supplies have
passed through their power-on reset threshold voltages.
Once initialized and configured, use the power calculator to
estimate current drain on these supplies.
For more information on V
mode, refer to Chapter 3 in the Virtex-II Pro Platform FPGA
User Guide.
XAPP689, “Managing Ground Bounce in Large FPGAs,” to
determine the number of simultaneously switching outputs
allowed per bank at the package level.
Changes in V
should take place at a rate no faster than 10 mV per milli-
second.
Recommended practices that can help reduce jitter and
period distortion are described in Xilinx Answer Record
13756.
1050
250
100
shows the minimum current required by Virtex-II Pro
1250
250
100
CCAUX
voltage beyond 200 mV peak-to-peak
1700
250
100
CCAUX
TBD
250
100
, V
CCO
Table 5
, and configuration
TBD
250
100
are met, the
Units
mA
mA
mA
5