XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 98

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Virtex-II Pro Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted
Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM
Table 46: Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM
DS083-3 (v2.12) November 11, 2003
Advance Product Specification
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
3. DCM output jitter is already included in the timing calculation.
Input Setup and Hold Time Relative to
Global Clock Input Signal for LVCMOS25
Standard.
For data input with different standards,
adjust the setup time delay by the values
shown in IOB Input Switching
Characteristics Standard
page
No Delay
Global Clock and IFF with DCM
relative to the Global Clock input signal with the slowest route and heaviest load.
22.
R
Description
Adjustments,
T
PSDCM
Symbol
/T
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
PHDCM
www.xilinx.com
1-800-255-7778
XC2VP100
XC2VP125
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Device
-7
Speed Grade
-6
-5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
41