XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 114

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Table 3: Virtex-II Pro Available I/Os and RocketIO MGT Pins per Device/Package Combination (Continued)
Virtex-II Pro Pin Definitions
This section describes the pinouts for Virtex-II Pro devices
in the following packages:
•
•
All of the devices supported in a particular package are
pinout-compatible and are listed in the same table (one
Pin Definitions
Table 4
Table 4: Virtex-II Pro Pin Definitions
DS083-4 (v2.5.5) August 25, 2003
Advance Product Specification
Virtex-II Pro
User I/O Pins
IO_LXXY_#
Dual-Function Pins
IO_LXXY_#/ZZZ
XC2VP100
XC2VP125
Device
FG256, FG456, and FG676: wire-bond fine-pitch BGA
of 1.00 mm pitch
FF672, FF896, FF1148, FF1152, FF1517, FF1696,
and FF1704: flip-chip fine-pitch BGA of 1.00 mm pitch
Pin Name
provides a description of each pin type listed in Virtex-II Pro pinout tables.
R
User I/Os &
Differential
Differential
MGT Pins
RocketIO
MGT Pins
MGT Pins
User I/Os
User I/Os
RocketIO
RocketIO
Available
Available
I/O Pairs
I/O Pairs
Input/Output All user I/O pins are capable of differential signalling and can implement LVDS, ULVDS,
Direction
FG256
-
-
-
-
-
-
BLVDS, LVPECL, or LDT pairs. Each user I/O is labeled “IO_LXXY_#”, where:
The dual-function pins are labelled “IO_LXXY_#/ZZZ”, where ZZZ can be one of the
following pins:
Per Bank - VRP, VRN, or VREF
Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, D0/DIN – D7, RDWR_B, or CS_B
IO indicates a user I/O pin.
LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for
the positive and negative sides of the differential pair.
# indicates the bank number (0 through 7)
FG456
-
-
-
-
-
-
FG676
www.xilinx.com
1-800-255-7778
FF672
-
-
-
-
-
-
table per package). Pins that are not available for smaller
devices are listed in right-hand columns.
Each device is split into eight I/O banks to allow for flexibility
in the choice of I/O standards. Global pins, including JTAG,
configuration, and power/ground pins, are listed at the end
of each table.
All Virtex-II Pro pinout tables are available on the distribu-
tion CD-ROM, or on the web (at
Virtex-II Pro Package
Virtex-II Pro™ Platform FPGAs: Pinout Information
FF896
-
-
-
-
-
-
Description
Table 4
FF1152 FF1148
-
-
-
-
-
-
provides definitions for all pin types.
-
-
-
-
-
-
http://www.xilinx.com
FF1517 FF1704 FF1696
-
-
-
-
-
-
1040
1040
180
512
180
512
1164
1200
572
590
0
0
).
3