XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 84

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Table 30: IOB Output Switching Characteristics Standard Adjustments (Continued)
DS083-3 (v2.12) November 11, 2003
Advance Product Specification
Standard-specific adjustments for
output delays terminating at pads
(based on standard capacitive load,
Csl)
R
Description
Output Delay Adjustments
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OHSTL_IV_DCI_18
OHSTL_III_DCI_18
T
T
T
OLVCMOS18_F16
OLVCMOS15_S12
OLVCMOS15_S16
OLVCMOS15_F12
OLVCMOS15_F16
OHSTL_II_DCI_18
T
T
OHSTL_I_DCI_18
OLVCMOS15_S2
OLVCMOS15_S4
OLVCMOS15_S6
OLVCMOS15_S8
T
OSSTL18_II_DCI
OLVCMOS15_F2
OLVCMOS15_F4
OLVCMOS15_F6
OLVCMOS15_F8
OLVDCI_DV2_25
OLVDCI_DV2_18
OLVDCI_DV2_15
T
OSSTL18_I_DCI
T
OHSTL_IV_DCI
OSSTL2_II_DCI
OHSTL_III_DCI
OSSTL2_I_DCI
T
OHSTL_II_DCI
T
T
OHSTL_I_DCI
T
T
T
T
OLVPECL_25
OGTLP_DCI
OSSTL18_II
Symbol
OSSTL18_I
OGTL_DCI
OLVDCI33
OLVDCI25
OLVDCI18
OLVDCI15
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
1-800-255-7778
LVCMOS15, Slow, 2 mA
LVCMOS15, Fast, 2 mA
HSTL_IV_DCI_18
HSTL_III_DCI_18
HSTL_II_DCI_18
HSTL_I_DCI_18
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
SSTL18_II_DCI
SSTL18_I_DCI
HSTL_IV_DCI
SSTL2_II_DCI
HSTL_III_DCI
SSTL2_I_DCI
HSTL_II_DCI
HSTL_I_DCI
LVPECL_25
GTLP_DCI
SSTL18_II
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
SSTL18_I
Standard
GTL_DCI
16 mA
12 mA
16 mA
12 mA
16 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
-7
Speed Grade
0.12
7.12
4.93
3.24
2.93
1.51
1.47
2.60
1.90
0.75
1.08
0.29
0.32
0.83
0.64
0.75
1.15
0.07
0.34
0.69
1.39
2.71
0.63
0.54
0.36
2.08
0.63
0.28
0.40
1.70
0.56
0.56
0.19
0.92
0.51
0.62
0.28
-6
0.13
7.83
5.42
3.56
3.23
1.66
1.62
2.86
2.09
0.82
1.19
0.32
0.35
0.91
0.71
0.82
1.26
0.08
0.38
0.76
1.53
2.98
0.69
0.60
0.40
2.29
0.70
0.31
0.44
1.87
0.61
0.61
0.21
1.01
0.56
0.68
0.31
-5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
27