XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 109

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Revision History
52
05/27/03
08/25/03
09/10/03
Date
Version
2.10
2.8
2.9
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Updated time and frequency parameters as per speedsfile v1.78.
Table
Corrected I
Table
XC2VP20. Added footnote specifying parameters are for Commercial Grade parts.
Table
Table
Changed V
LVCMOS18 from 20% V
Table
explanatory text above table.
Table 12
from XC2VP7FF672-6 to XC2VP20FF1152-6.
Table
speed grade and Production for the -5 speed grade.
Removed former Table 32, Standard Capacitive Loads.
Table
Table
Jitter Calculator.
Added
Table
Table
version) due to a document compilation error. The concatenated full data sheet version
was not affected. These parameters have been restored.
Updated time and frequency parameters as per speedsfile v1.81.
Table
Table
Table 44
specified a capacitive load parameter.
Table
erroneously omitted from the full data sheet file (all four modules concatenated),
though not from the stand-alone Module 3 file. The omitted parameters have been
restored.
Table 55
labeled. Previously expressed in nanoseconds, but labeled picoseconds.
Figure 6: Added note to figure regarding termination resistors.
Table
Figure
must be held to a constant DC level during and after configuration.
Table
constant DC level during and after configuration.
3: Added values for I
4: Updated/Added Typ and Max quiescent current values for XC2VP7 and
5: Added footnote specifying parameters are for Commercial Grade parts.
6: Corrected V
10: Corrected LVPECL_25 Min and Max values for V
14: Updated to show devices XC2VP7 and XC2VP20 as Preliminary for the -6
43: Updated T
50: Modified footnote referenced at CLKFX/CLKFX180 to point to the online
1: Footnote (2) rewritten to specify “one or more banks.”
48: Some DCM parameters were erroneously missing from v2.8 (single-module
1: Footnote (2) rewritten to specify “one or more banks.”
2: Added footnote referring to XAPP659 for 3.3V I/O operation.
48: Due to a document compilation error in v2.8, some DCM parameters were
5: Added I
40: Added footnote indicating that mode pins M0, M1, and M2 must be held to a
7: Changed representation of mode pins M0, M1, and M2 indicating that they
Figure 6
and
and
and
CCINTQ
IL
(Min) for all standards to –0.2V. Corrected V
Table 13
Table
Table
and accompanying procedure for measuring standard adjustments.
CCINTMIN
www.xilinx.com
(Table
1-800-255-7778
45: Revised test setup footnote to refer to
57: Corrected parameters to expression in picoseconds, as
TAPTCK
IH
(pin-pin and reg-reg performance): Changed device specified
(Max) for LVTTL and LVCMOS33 standards from 3.6V to 3.45V.
CCO
4) and I
for XC2VP30 device.
REF
from 4.0 ns to 5.5 ns.
to 30% V
, I
L
, I
CCINTMIN
RPU
Revision
CCO
, I
RPD
.
(Table
5) for XC2VP20 to 600 mA.
DS083-3 (v2.12) November 11, 2003
IL
Advance Product Specification
IH
(Max) for LVCMOS15 and
and V
Figure
IL
. Added
6. Previously
R