XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 112

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

DS083-4 (v2.5.5) August 25, 2003
This document provides
binations and Maximum I/Os
tions, followed by pinout tables, for these packages:
•
•
•
•
•
Virtex-II Pro Device/Package Combinations and Maximum I/Os
Wire-bond and flip-chip packages are available.
Table 2
wire-bond and flip-chip packages, respectively.
•
•
Table 2: Flip-Chip Packages Information
Table 3
of differential I/O pairs for each Virtex-II Pro device/package combination. The number of I/Os per package includes all user
I/Os except the fifteen control pins (CCLK, DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO, TMS,
HSWAP_EN, DXN, DXP, AND RSVD) and the nine (per transceiver) RocketIO MGT pins (TXP, TXN, RXP, RXN,
AVCCAUXTX, AVCCAUXRX, VTTX, VTRX, and GNDA). The number of transceivers in the device is the number of
RocketIO MGT pins in
Table 3: Virtex-II Pro Available I/Os and RocketIO MGT Pins per Device/Package Combination
DS083-4 (v2.5.5) August 25, 2003
Advance Product Specification
Pitch (mm)
Size (mm)
Maximum I/Os
Virtex-II Pro
XC2VP2
Device
FG256 Fine-Pitch BGA Package
FG456 Fine-Pitch BGA Package
FG676 Fine-Pitch BGA Package
FF672 Flip-Chip Fine-Pitch BGA Package
FF896 Flip-Chip Fine-Pitch BGA Package
FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).
FF denotes flip-chip fine-pitch BGA (1.00 mm pitch)
Package
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show the maximum number of user I/Os possible in
shows the number of available I/Os, the number of RocketIO™ multi-gigabit transceiver (MGT) pins, and the number
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
User I/Os &
Differential
MGT Pins
RocketIO
MGT Pins
User I/Os
RocketIO
Available
I/O Pairs
27 x 27
FF672
Table 3
1.00
396
Virtex-II Pro Device/Package Com-
R
and
divided by nine.
FG256
140
36
68
Virtex-II Pro Pin Defini-
31 x 31
FF896
1.00
556
FG456
156
36
76
Table 1
FG676
FF1152
35 x 35
1.00
0
0
644
-
-
-
www.xilinx.com
1-800-255-7778
and
298
0
FF672
204
100
36
Virtex-II Pro™ Platform FPGAs:
Pinout Information
Advance Product Specification
•
•
•
•
•
For device pinout diagrams and layout guidelines, refer to
the
age pinout files are also available for download from the Xil-
inx website (www.xilinx.com).
.
Table 1: Wire-Bond Packages Information
Pitch (mm)
Size (mm)
Maximum I/Os
Virtex-II Pro Package
FF1148
35 x 35
Virtex-II Pro Platform FPGA User
FF1152 Flip-Chip Fine-Pitch BGA Package
FF1148 Flip-Chip Fine-Pitch BGA Package
FF1517 Flip-Chip Fine-Pitch BGA Package
FF1704 Flip-Chip Fine-Pitch BGA Package
FF1696 Flip-Chip Fine-Pitch BGA Package
Package
1.00
812
FF896
-
-
-
FF1152 FF1148
-
-
-
FF1517
40 x 40
1.00
964
17 x 17
FG256
1.00
140
-
-
-
42.5 x 42.5
FF1517 FF1704 FF1696
FF1704
1040
1.00
23 x 23
FG456
-
-
-
1.00
248
Guide. ASCII pack-
-
-
-
42.5 x 42.5
FF1696
26 x 26
FG676
1200
1.00
1.00
412
-
-
-
1