XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 43

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
Table 17: Dual-Port Mode Configurations
34
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Figure 38: 18 Kb Block SelectRAM+ Memory in
DI
DIP
ADDR
WE
EN
SSR
CLK
18-Kbit Block SelectRAM
512 x 36
512 x 36
16K x 1
16K x 1
1K x 18
1K x 18
Single-Port Mode
8K x 2
8K x 2
4K x 4
4K x 4
2K x 9
2K x 9
512 x 36
DOP
16K x 1
1K x 18
1K x 18
8K x 2
8K x 2
4K x 4
4K x 4
2K x 9
2K x 9
DO
DS031_10_102000
www.xilinx.com
1-800-255-7778
512 x 36
16K x 1
1K x 18
4K x 4
8K x 2
2K x 9
4K x 4
2K x 9
Dual-Port Configuration
As a dual-port RAM, each port of block SelectRAM+ has
access to a common 18 Kb memory resource. These are
fully synchronous ports with independent control signals for
each port. The data widths of the two ports can be config-
ured independently, providing built-in bus-width conversion.
Table 17
ports A and B.
If both ports are configured in either 2K x 9-bit, 1K x 18-bit,
or 512 x 36-bit configurations, the 18 Kb block is accessible
from port A or B. If both ports are configured in either 16K x
1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the 16 K-bit
block is accessible from Port A or Port B. All other configu-
rations result in one port having access to an 18 Kb memory
block and the other port having access to a 16 K-bit subset
of the memory block equal to 16 Kbs.
illustrates the different configurations available on
512 x 36
16K x 1
1K x 18
2K x 9
8K x 2
4K x 4
512 x 36
16K x 1
1K x 18
DS083-2 (v2.9) October 14, 2003
8K x 2
Advance Product Specification
512 x 36
16K x 1
R