XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 5

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Architecture
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Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows:
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These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended I/O standards:
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1. Refer to
2. Refer to
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Virtual mode memory management unit (MMU)
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OCM controllers provide dedicated interfaces between
Block SelectRAM+ memory and processor block
instruction and data paths for high-speed access
PowerPC timer facilities
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Debug Support
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Two hardware interrupt levels support
Advanced power management support
Input block with an optional single data rate (SDR) or
double data rate (DDR) register
Output block with an optional SDR or DDR register and
an optional 3-state buffer to be driven directly or
through an SDR or DDR register
Bidirectional block (any combination of input and output
configurations)
LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
PCI-X compatible (133 MHz and 66 MHz) at 3.3V
PCI compliant (66 MHz and 33 MHz) at 3.3V
GTL and GTLP
HSTL (1.5V and 1.8V, Class I, II, III, and IV)
SSTL (1.8V and 2.5V, Class I and II)
16 KB array Instruction Cache Unit (ICU), 16 KB
array Data Cache Unit (DCU)
Operand forwarding during instruction cache line fill
Copy-back or write-through DCU strategy
Doubleword instruction fetch from cache improves
branch latency
Translation of the 4 GB logical address space into
physical addresses
Software control of page replacement strategy
Supports multiple simultaneous page sizes ranging
from 1 KB to 16 MB
64-bit time base
Programmable interval timer (PIT)
Fixed interval timer (FIT)
Watchdog timer (WDT)
Internal debug mode
External debug mode
Debug Wait mode
Real Time Trace debug mode
Enhanced debug support with logical operators
Instruction trace and trace-back support
Forward or backward trace
XAPP659
XAPP653
for more information.
for more information.
(2)
(1)
www.xilinx.com
(2)
1-800-255-7778
The DCI I/O feature automatically provides on-chip termina-
tion for each single-ended I/O standard.
The IOB elements also support the following differential sig-
naling I/O standards:
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Two adjacent pads are used for each differential pair. Two or
four IOB blocks connect to one switch matrix to access the
routing resources.
Configurable Logic Blocks (CLBs)
CLB resources include four slices and two 3-state buffers.
Each slice is equivalent and contains:
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The function generators F & G are configurable as 4-input
look-up tables (LUTs), as 16-bit shift registers, or as 16-bit
distributed SelectRAM+ memory.
In addition, the two storage elements are either
edge-triggered D-type flip-flops or level-sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
Block SelectRAM+ Memory
The block SelectRAM+ memory resources are 18 Kb of
True Dual-Port RAM, programmable from 16K x 1 bit to
512 x 36 bit, in various depth and width configurations.
Each port is totally synchronous and independent, offering
three "read-during-write" modes. Block SelectRAM+ mem-
ory is cascadable to implement large embedded storage
blocks. Supported memory configurations for dual-port and
single-port modes are shown in
Table 2: Dual-Port and Single-Port Configurations
18 X 18 Bit Multipliers
A multiplier block is associated with each SelectRAM+
memory block. The multiplier block is a dedicated
18 x 18-bit 2s complement signed multiplier, and is opti-
LVDS and Extended LVDS (2.5V)
BLVDS (Bus LVDS)
ULVDS
LDT
LVPECL (2.5V)
Two function generators (F & G)
Two storage elements
Arithmetic logic gates
Large multiplexers
Wide function capability
Fast carry look-ahead chain
Horizontal cascade chain (OR gate)
16K x 1 bit
8K x 2 bits
4K x 4 bits
2K x 9 bits
DS083-1 (v2.4.2) August 25, 2003
Advance Product Specification
Table
2.
512 x 36 bits
1K x 18 bits
R