XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 28

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Table 7: Summary of Voltage Supply Requirements for
All Input and Output Standards
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
I/O Standard
LVTTL
LVCMOS33
LVDCI_33
PCIX
PCI33_3
PCI66_3
LVDS_25
LVDSEXT_25
LDT_25
ULVDS_25
BLVDS_25
LVPECL_25
SSTL2_I
SSTL2_II
LVCMOS25
LVDCI_25
LVDCI_DV2_25
LVDS_25_DCI
LVDSEXT_25_DCI
SSTL2_I_DCI
SSTL2_II_DCI
LVDS_25_DT
LVDSEXT_25_DT
LDT_25_DT
ULVDS_25_DT
HSTL_III_18
HSTL_IV_18
HSTL_I_18
HSTL_II_18
SSTL18_I
SSTL18_II
LVCMOS18
LVDCI_18
LVDCI_DV2_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
HSTL_I_DCI_18
HSTL_II_DCI_18
SSTL18_I_DCI
SSTL18_II_DCI
(2)
(1)
(2)
(2)
(1)
(1)
R
Output
3.3
2.5
1.8
V
CCO
Note (3)
Note (3)
Input
3.3
2.5
1.8
Input
V
1.25
1.25
1.25
1.25
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
1.1
1.1
0.9
0.9
0.9
0.9
1.1
1.1
0.9
0.9
0.9
0.9
REF
Output
Termination Type
Series
Series
Series
Series
Series
Single
Split
Split
Split
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Single
Single
Input
Split
Split
Split
Split
Split
Split
Split
Split
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
www.xilinx.com
1-800-255-7778
Table 7: Summary of Voltage Supply Requirements for
All Input and Output Standards (Continued)
Digitally Controlled Impedance (DCI)
Today’s chip output signals with fast edge rates require ter-
mination to prevent reflections and maintain signal integrity.
High pin count packages (especially ball grid arrays) can
not accommodate external termination resistors.
Virtex-II Pro XCITE DCI provides controlled impedance
drivers and on-chip termination for single-ended and differ-
ential I/Os. This eliminates the need for external resistors
and improves signal integrity. The DCI feature can be used
on any IOB by selecting one of the DCI I/O standards.
When applied to inputs, DCI provides input parallel termina-
tion. When applied to outputs, DCI provides controlled
impedance drivers (series termination) or output parallel
termination.
DCI operates independently on each I/O bank. When a DCI
I/O standard is used in a particular I/O bank, external refer-
ence resistors must be connected to two dual-function pins
on the bank. These resistors, voltage reference of N transis-
tor (VRN) and the voltage reference of P transistor (VRP)
are shown in
Virtex-II Pro™ Platform FPGAs: Functional Description
Notes:
1.
2.
3.
4.
I/O Standard
HSTL_III
HSTL_IV
HSTL_I
HSTL_II
LVCMOS15
LVDCI_15
LVDCI_DV2_15
GTLP_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI
HSTL_II_DCI
GTL_DCI
GTLP
GTL
See application note
See application note
Pin voltage must not exceed V
N/R = no requirement.
Figure
Output
N/R
1.5
1.2
17.
XAPP659
XAPP653
V
CCO
Note (3)
Note (3)
Input
1.5
1.2
CCO
for more detailed information.
for more detailed information.
.
Input
V
0.75
0.75
0.75
0.75
N/R
N/R
N/R
0.9
0.9
0.9
0.9
0.8
0.8
REF
1
1
Output
Termination Type
Series
Series
Single
Single
Single
Split
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Single
Single
Single
Single
Input
Split
Split
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
19