XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 55

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Revision History
Bitstream Encryption
Virtex-II Pro devices have an on-chip decryptor using one or
two sets of three keys for triple-key Data Encryption Stan-
dard (DES) operation. Xilinx software tools offer an optional
encryption of the configuration data (bitstream) with a tri-
ple-key DES determined by the designer.
The keys are stored in the FPGA by JTAG instruction and
retained by a battery connected to the V
device is not powered. Virtex-II Pro devices can be config-
ured with the corresponding encrypted bitstream, using any
of the configuration modes described previously.
A detailed description of how to use bitstream encryption is
provided in the Virtex-II Pro Platform FPGA User Guide.
Your local FAE can also provide specific information on this
feature.
Revision History
This section records the change history for this module of the data sheet.
46
01/31/02
06/13/02
09/03/02
09/27/02
11/20/02
12/03/02
01/20/03
03/24/03
Date
Version
2.5.1
1.0
2.0
2.1
2.2
2.3
2.4
2.5
Initial Xilinx release.
New Virtex-II Pro family members. New timing parameters per speedsfile v1.62.
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Revised
Updated
Added
use of I/O standards.
In section Overview, corrected max number of MGTs from 16 to 24.
In section
implementation of 3.3V I/O standards.
Table
Table
Table
Added mention of LVTTL and PCI with respect to SelectIO-Ultra configurations. See
section
Added qualification to features vs. Virtex-II (open-drain output pin TDO does not have
internal pullup resistor)
Table 7: Added HSTL18 (I, II, III, & IV) and HSTL18_DCI (I,II, III & IV) to 1.8V VCCO
row. [Table deleted in v2.6.]
Table 8: Numerous revisions. [Table deleted in v2.6.]
Table
and SSTL18_II_DCI respectively.
Figure
BATT
3: Added rows for LVTTL, LVCMOS33, and PCI-X.
8: Added LVTTL and LVCMOS33 to compatible 3.3V cells. [Table deleted in v2.6.]
28: Correct bitstream lengths.
5: Corrected I/O standard names SSTL18_I and SSTL18_II to SSTL18_I_DCI
52, text below: Corrected wording of criteria for clock switching.
Figure
Input/Output Individual Options
Reset
Table
Input/Output Blocks
pin, when the
19,
8, which lists compatible input standards. [Table deleted in v2.6.]
and
Figure
www.xilinx.com
1-800-255-7778
Power
20, and
sections.
Partial Reconfiguration
Partial reconfiguration of Virtex-II Pro devices can be
accomplished in either Slave SelectMAP mode or Bound-
ary-Scan mode. Instead of resetting the chip and doing a
full configuration, new data is loaded into a specified area of
the chip, while the rest of the chip remains in operation.
Data is loaded on a column basis, with the smallest load unit
being a configuration “frame” of the bitstream (device size
dependent).
Partial reconfiguration is useful for applications that require
different designs to be loaded into the same area of a chip,
or that require the ability to change portions of a design
without having to reset or reconfigure the entire chip.
For more information on Partial Reconfiguration in
Virtex-II Pro devices, please refer to Xilinx Application Note
XAPP290
(IOBs), added references to XAPP653 regarding
Figure
Revision
, Two Flows for Partial Reconfiguration.
and
21, which provide examples illustrating the
Figure
13.
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
R