XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 82

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVCMOS25 with 12 mA drive and fast slew rate. For other standards,
adjust the delays by the values shown.
Table 30: IOB Output Switching Characteristics Standard Adjustments
DS083-3 (v2.12) November 11, 2003
Advance Product Specification
Standard-specific adjustments for
output delays terminating at pads
(based on standard capacitive load,
Csl)
R
Description
Output Delay Adjustments
T
T
T
T
OLVCMOS33_S2
T
T
T
T
T
T
T
T
T
T
OLVDSEXT_25
T
T
T
T
T
T
T
T
OHSTL_IIII_18
T
T
OHSTL_IV_18
T
T
T
T
OHSTL_II_18
T
T
OLVTTL_S12
OLVTTL_S16
OLVTTL_S24
OLVTTL_F12
OLVTTL_F16
OLVTTL_F24
T
OHSTL_I_18
OBLVDS_25
OULVDS_25
T
OLVTTL_S2
OLVTTL_S4
OLVTTL_S6
OLVTTL_S8
OLVTTL_F2
OLVTTL_F4
OLVTTL_F6
OLVTTL_F8
Symbol
OHSTL_IIII
OLVDS_25
T
OHSTL_IV
OSSTL2_II
OPCI33_3
OPCI66_3
OSSTL2_I
T
OLDT_25
OHSTL_II
T
OHSTL_I
OGTLP
OPCIX
OGTL
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
1-800-255-7778
LVCMOS33, Slow, 2 mA
LVTTL, Slow, 2 mA
PCI, 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
LVTTL, Fast, 2 mA
HSTL_IV_18
HSTL_III_18
HSTL_II_18
HSTL_I_18
LVDSEXT
Standard
SSTL2_II
HSTL_IV
HSTL_III
SSTL2_I
HSTL_II
HSTL_I
ULVDS
BLVDS
12 mA
16 mA
24 mA
12 mA
16 mA
24 mA
PCI-X
LVDS
GTLP
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
GTL
LDT
-7
Speed Grade
–0.01
0.01
0.15
0.14
0.00
0.14
0.75
0.79
0.79
1.41
2.69
0.64
0.35
0.35
0.17
0.64
0.35
0.41
0.22
0.72
0.25
6.24
3.55
2.60
1.69
1.18
0.53
0.42
5.09
2.24
1.26
0.46
0.27
0.06
6.23
-6
–0.01
0.01
0.16
0.16
0.00
0.16
0.83
0.87
0.87
1.55
2.96
0.70
0.38
0.39
0.19
0.70
0.38
0.45
0.24
0.79
0.27
6.86
3.91
2.86
1.86
1.29
0.58
0.47
5.59
2.46
1.39
0.51
0.30
0.07
6.86
-5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25