XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 25

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
16
Figure 13: LVTTL, LVCMOS, or PCI SelectIO-Ultra
Program
Delay
OBUF
registers
Shared
Program
Current
by all
(O/T) CLK1
(O/T) CLK2
V CCO
IBUF
(O/T) CE
(O/T) 1
(O/T) 2
V CCO
REV
SR
Standard
Clamp
Diode
Figure 12: Register / Latch Configuration in an IOB Block
V CCO
40KΩ –
40KΩ –
120KΩ
120KΩ
Keeper
Weak
V CCAUX = 2.5V
V CCINT = 1.5V
DS083-2_07_101801
D1
CE
CK1
D2
CE
CK2
SR REV
SR REV
www.xilinx.com
FF
LATCH
FF
LATCH
1-800-255-7778
PAD
Q1
Q2
Attribute INIT1
Attribute INIT1
Input/Output Individual Options
Each device pad has optional pull-up/pull-down resistors
and weak-keeper circuit in the LVTTL, LVCMOS, and PCI
SelectIO-Ultra configurations, as illustrated in
Values of the optional pull-up and pull-down resistors fall
within a range of 40 KΩ to 120 KΩ when V
2.38V to 2.63V only). The clamp diodes are always present,
even when power is not.
The optional weak-keeper circuit is connected to each user
I/O pad. When selected, the circuit monitors the voltage on
the pad and weakly drives the pin High or Low. If the pin is
connected to a multiple-source signal, the weak-keeper
holds the signal in its last state if all drivers are disabled.
Maintaining a valid logic level in this way eliminates bus
chatter. An enabled pull-up or pull-down overrides the
weak-keeper circuit.
LVCMOS25 sinks and sources current up to 24 mA. The
current is programmable (see
slew rate controls for each output driver minimize bus tran-
sients. For LVDCI and LVDCI_DV2 standards, drive strength
and slew rate controls are not available.
DDR MUX
FF1
FF2
INIT0
SRHIGH
SRLOW
INIT0
SRHIGH
SRLOW
Reset Type
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
SYNC
ASYNC
Table
DS031_25_110300
(OQ or TQ)
6). Drive strength and
CCO
= 2.5V (from
Figure
13.
R