XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 54

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

IEEE 1532 standard for In-System Configurable (ISC)
devices. The IEEE 1532 standard is backward compliant
with the IEEE 1149.1-1993 TAP and state machine. The
IEEE Standard 1532 for In-System Configurable (ISC)
devices is intended to be programmed, reprogrammed, or
Table 27: Virtex-II Pro Configuration Mode Pin Settings
Table 28
each device.
Table 28: Virtex-II Pro Bitstream Lengths
Configuration Sequence
The configuration of Virtex-II Pro devices is a three-phase
process. First, the configuration memory is cleared. Next,
configuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
Configuration is automatically initiated on power-up unless
it is delayed by the user. The INIT_B pin can be held Low
using an open-drain driver. An open-drain is required since
INIT_B is a bidirectional open-drain pin that is held Low by a
Virtex-II Pro FPGA device while the configuration memory
is being cleared. Extending the time that the pin is Low
causes the configuration sequencer to wait. Thus, configu-
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
Notes:
1. The HSWAP_EN pin controls the pullups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin controls
2. Daisy chaining is possible only in modes where Serial D
Master Serial
Slave Serial
Master SelectMAP
Slave SelectMAP
Boundary Scan
whether or not the pullups are used.
support daisy chaining of downstream devices.
Configuration Mode
XC2VP100
XC2VP125
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
lists the total number of bits required to configure
Device
R
(1)
Number of Configuration
11,589,984
15,868,256
19,021,408
26,099,040
34,292,832
43,602,784
1,305,440
3,006,560
4,485,472
8,214,624
M2
0
1
0
1
1
Bits
M1
0
1
1
1
0
www.xilinx.com
1-800-255-7778
OUT
is used. For example, in SelectMAP modes, the first device does NOT
M0
0
1
1
0
1
tested on the board via a physical and logical protocol. Con-
figuration through the boundary-scan port is always avail-
able, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes.
ration is delayed by preventing entry into the phase where
data is loaded.
The configuration process can also be initiated by asserting
the PROG_B pin. The end of the memory-clearing phase is
signaled by the INIT_B pin going High, and the completion
of the entire process is signaled by the DONE pin going
High. The Global Set/Reset (GSR) signal is pulsed after the
last frame of configuration data is written but before the
start-up sequence. The GSR signal resets all flip-flops on
the device.
The default start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary. One CCLK cycle later, the Global Write Enable (GWE)
signal is released. This permits the internal storage ele-
ments to begin changing state in response to the logic and
the user clock.
The relative timing of these events can be changed via con-
figuration options in software. In addition, the GTS and
GWE events can be made dependent on the DONE pins of
multiple devices all going High, forcing the devices to start
synchronously. The sequence can also be paused at any
stage, until lock has been achieved on any or all DCMs, as
well as DCI.
Readback
In this mode, configuration data from the Virtex-II Pro FPGA
device can be read back. Readback is supported only in the
SelectMAP (master and slave) and Boundary Scan mode.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed SelectRAM+, and
block RAM resources. This capability is used for real-time
debugging. For more detailed configuration information, see
the Virtex-II Pro Platform FPGA User Guide.
Virtex-II Pro™ Platform FPGAs: Functional Description
CCLK Direction
Out
Out
N/A
In
In
Data Width
1
1
8
8
1
Serial D
Yes
Yes
No
No
No
OUT
(2)
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