ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet
ep2a40b724i8
Manufacturer Part Number
ep2a40b724i8
Description
Programmable Logic Device Family
Manufacturer
Altera Corporation
Datasheet
1.EP2A40B724I8.pdf
(99 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2A40B724I8
Manufacturer:
ALTERA
Quantity:
3 000
Features...
Altera Corporation
DS-APEXII-3.0
August 2002, ver. 3.0
Programmable logic device (PLD) manufactured using a 0.15- m all-
layer copper-metal fabrication process (up to eight layers of metal)
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High-density architecture
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Low-power operation design
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1-gigabit per second (Gbps) True-LVDS
current mode logic (PCML), and HyperTransport
Clock-data synchronization (CDS) in True-LVDS interface to
correct any fixed clock-to-data skew
Enables common networking and communications bus I/O
standards such as RapidIO
Level 4
Support for high-speed external memory interfaces, including
zero bus turnaround (ZBT), quad data rate (QDR), and double
data rate (DDR) static RAM (SRAM), and single data rate (SDR)
and DDR synchronous dynamic RAM (SDRAM)
30% to 40% faster design performance than APEX
devices on average
Enhanced 4,096-bit embedded system blocks (ESBs)
implementing first-in first-out (FIFO) buffers, Dual-Port+ RAM
(bidirectional dual-port RAM), and content-addressable
memory (CAM)
High-performance, low-power copper interconnect
Fast parallel byte-wide synchronous device configuration
Look-up table (LUT) logic available for register-intensive
functions
1,900,000 to 5,250,000 maximum system gates (see
Up to 67,200 logic elements (LEs)
Up to 1,146,880 RAM bits that can be used without reducing
available logic
1.5-V supply voltage
Copper interconnect reduces power consumption
MultiVolt
interfaces
ESBs offer programmable power-saving mode
®
TM
I/O support for 1.5-V, 1.8-V, 2.5-V, and 3.3-V
TM
, CSIX, Utopia IV, and POS-PHY
Programmable Logic
TM
, LVPECL, pseudo
Device Family
TM
APEX II
TM
Table
interface
Data Sheet
20KE
1)
1
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