ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 41

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
Figure 27. Column IOE Connection to the Interconnect
Any LE or ESB can drive
a column pin through a
row, column, and MegaLAB
interconnect.
An LE or ESB can drive a
pin through a local
interconnect for faster
clock-to-output times.
Row Interconnect
FastRow interconnects connect a column I/O pin directly to the LAB local
interconnect within two MegaLAB structures. This feature provides fast
setup times for pins that drive high fan-outs with complex logic, such as
PCI designs. For fast bidirectional I/O timing, LE registers using local
routing can improve setup times and OE timing.
APEX II devices have a peripheral control bus made up of 12 signals that
drive the IOE control signals. The peripheral bus is composed of six
output enables, OE[5:0] and six clock enables, CE[5:0]. These twelve
signals can be driven from internal logic or from the Fast I/O signals.
Table 7
lists the peripheral control signal destinations.
Each IOE can drive column and FastRow
interconnects. Each IOE data and
OE signal is driven by local interconnect.
IOE
MegaLAB Interconnect
LAB
APEX II Programmable Logic Device Family Data Sheet
IOE
Column Interconnect
41