ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 45

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
Figure 29. APEX II IOE in DDR Input I/O Configuration
Column, Row
Interconnect
or Local
12 Peripheral
Signals
Dedicated
Clocks
Eight
Chip-Wide Reset
When using the IOE for DDR inputs, the two input registers are used to
clock double rate input data on alternating edges. An input latch is also
used within the IOE for DDR input acquisition. The latch holds the data
that is present during the clock high times. This allows both bits of data to
be synchronous to the same clock edge (either rising or falling).
shows an IOE configured for DDR input.
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from LEs on rising clock edges. These
register outputs are multiplexed by the clock to drive the output pin at a
while the other output register clocks the second bit out on the clock low
time.
Enable Delay
2 rate. One output register clocks the first bit out on the clock high time,
Input Clock
Figure 30
shows the IOE configured for DDR output.
APEX II Programmable Logic Device Family Data Sheet
Input Register
Input Register
CLRN/PRN
D
CLRN/PRN
D
ENA
ENA
Q
Q
D
CLRN/PRN
ENA
Input Pin to Input
Register Delay
Latch
Q
VCCIO
VCCIO
Optional
PCI Clamp
Bus-Hold
Circuit
Programmable
Pull-Up
Figure 29
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