ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 2

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

APEX II Programmable Logic Device Family Data Sheet
Notes to
(1)
(2)
(3)
(4)
...and More
Features
2
Maximum gates
Typical gates
LEs
RAM ESBs
Maximum RAM bits
True-LVDS channels
Flexible-LVDS
True-LVDS PLLs
General-purpose PLL outputs
Maximum user I/O pins
Table 1. APEX II Device Features
Each device has 36 input channels and 36 output channels.
EP2A15 and EP2A25 devices have 56 input and 56 output channels; EP2A40 and EP2A70 devices have 88 input and
88 output channels.
PLL: phase-locked loop. True-LVDS PLLs are dedicated to implement True-LVDS functionality.
Two internal outputs per PLL are available. Additionally, the device has one external output per PLL pair (two
external outputs per device).
Table
TM
Feature
1:
channels
(3)
(2)
(4)
I/O features
–
–
–
–
–
–
–
–
–
–
–
Up to 380 Gbps of I/O capability
1-Gbps True-LVDS, LVPECL, PCML, and HyperTransport
support on 36 input and 36 output channels that feature clock
synchronization circuitry and independent clock multiplication
and serialization/deserialization factors
Common networking and communications bus I/O standards
such as RapidIO, CSIX, Utopia IV, and POS-PHY Level 4 enabled
400-megabits per second (Mbps) Flexible-LVDS and
HyperTransport support on up to 88 input and 88 output
channels (input channels also support LVPECL)
Support for high-speed external memories, including ZBT, QDR,
and DDR SRAM, and SDR and DDR SDRAM
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
Compliant with 133-MHz PCI-X specifications
Support for other advanced I/O standards, including AGP, CTT,
SSTL-3 and SSTL-2 Class I and II, GTL+, and HSTL Class I and II
Six dedicated registers in each I/O element (IOE): two input
registers, two output registers, and two output-enable registers
Programmable bus hold feature
Programmable pull-up resistor on I/O pins available during
user mode
1,900,000
600,000
425,984
EP2A15
16,640
36
104
492
56
4
8
(1)
2,750,000
900,000
622,592
EP2A25
24,320
36
152
612
56
4
8
(1)
3,000,000
1,500,000
655,360
EP2A40
38,400
36
160
735
88
4
8
(1)
Altera Corporation
5,250,000
3,000,000
1,146,880
EP2A70
67,200
36
1,060
280
88
4
8
(1)