ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 44

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

APEX II Programmable Logic Device Family Data Sheet
Note to
(1)
44
Table 8. APEX II Programmable Delay Chain
This delay has four settings: off and three levels of delay.
Table
Input pin to logic array delay
Input pin to input register delay
Output propagation delay
Output enable register t
Output t
Output clock enable delay
Input clock enable delay
Logic array to output register delay
Programmable Delays
8:
ZX
delay
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay. Programmable
delays exist for decreasing input pin to logic array and IOE input register
delays. The Quartus II Compiler can program these delays automatically
to minimize setup time while providing a zero hold time. Delays are also
programmable for increasing the register to pin delays for output and/or
output enable registers. A programmable delay exists for increasing the
t
shows the programmable delays for APEX II devices.
The IOE registers in APEX II devices share the same source for clear or
preset. The designer can program preset and clear for each individual
IOE. The registers can be programmed to power up high or low after
configuration is complete. If programmed to power up low, an
asynchronous clear can control the registers. If programmed to power up
high, an asynchronous preset can control the registers. This feature
prevents the inadvertent activation of another device’s active-low input
upon power-up. If one register in an IOE uses a preset or clear signal then
all registers in the IOE must use that preset or clear signal.
Double Data Rate I/O
APEX II devices have six-register IOEs which support DDR interfacing by
clocking data on both positive and negative clock edges. The IOEs in
APEX II devices support DDR inputs, DDR outputs, and bidirectional
DDR modes.
ZX
CO
delay to the output pin, which is required for ZBT interfaces.
delay
(1)
Decrease input delay to internal cells
Decrease input delay to input register
Increase delay to output pin
Increase delay to output enable pin
Increase t
Increase output clock enable delay
Increase input clock enable delay
Decrease input delay to output register
Quartus II Logic Option
ZX
delay to output pin
Altera Corporation
Table 8