ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 81

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
t
t
t
t
SU
H
CO
LUT
Table 47. APEX II f
Symbol
MAX
LE register setup time before clock
LE register hold time before clock
LE register clock-to-output delay
LUT delay for data-in to data-out
LE Timing Parameters
Figure 42
IOE timing.
Figure 42. Synchronous External TIming Model
Notes to
(1)
(2)
(3)
Tables 47
minimum pulse-width timing parameters for the f
The output enable register is in the IOE and is controlled by the
“Fast Output Enable Register = ON” option in the Quartus II software.
The output register is in the IOE and is controlled by the
“Fast Output Register = ON” option in the Quartus II software.
The input register is in the IOE and is controlled by the “Fast Input Register = ON”
option in the Quartus II software.
Dedicated
Clock
Figure
shows the timing model for bi-directional, input, and output
through
42:
50
APEX II Programmable Logic Device Family Data Sheet
show APEX II LE, ESB, and routing delays and
Output IOE Register (2)
Input Register (3)
OE Register (1)
D
D
D
Parameter
CLRN
CLRN
CLRN
PRN
PRN
PRN
Q
Q
Q
t
t
XZ
ZX
t
OUTCO
MAX
t
t
INSU
INH
Bidirectional Pin
timing model.
81