ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 17

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ep2a40b724i8

Manufacturer Part Number
ep2a40b724i8
Description
Programmable Logic Device Family
Manufacturer
Altera Corporation
Datasheet

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Figure 8. APEX II LE Operating Modes
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
data1 (5)
data2 (5)
Normal Mode (1)
Arithmetic Mode
Counter Mode
LEs in normal mode support register packing.
There are two LAB-wide clock enables per LAB.
When using the carry-in in normal mode, the packed register feature is unavailable.
A register feedback multiplexer is available on LE1 of each LAB.
The DATA1 and DATA2 input signals can supply counter enable, up or down control, or register feedback signals for
LEs other than the second LE in a LAB.
The LAB-wide synchronous clear and LAB-wide synchronous load affect all registers in a LAB.
data3
(4)
data1
data2
data1
data2
data3
data4
Figure
Carry-In
Carry-In (3)
8:
Carry-In
3-Input
3-Input
LUT
LUT
3-Input
3-Input
4-Input
LUT
LUT
LUT
Cascade-In
Cascade-In
Carry-Out
Carry-Out
Cascade-In
Cascade-Out
Cascade-Out
Cascade-Out
LAB-Wide
Synchronous
Load (6)
APEX II Programmable Logic Device Family Data Sheet
LAB-Wide
Clock Enable (2)
LAB-Wide
Synchronous
Clear (6)
LAB-Wide
Clock Enable (2)
LAB-Wide
Clock Enable (2)
D
ENA
CLRN
PRN
D
ENA
CLRN
PRN
Q
ENA
D
Q
CLRN
PRN
Q
LE-Out
LE-Out
LE-Out
LE-Out
LE-Out
LE-Out
17

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