ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 84

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

APEX II Programmable Logic Device Family Data Sheet
Note to
(1)
84
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CH
CL
CLRP
PREP
ESBCH
ESBCL
ESBWP
ESBRP
INSU
INH
OUTCO
XZ
ZX
INSUPLL
INHPLL
OUTCOPLL
XZPLL
ZXPLL
Table 50. APEX II Minimum Pulse Width Timing Parameters
Table 51. APEX II External Timing Parameters
External timing parameters are factory tested, worst-case values specified by Altera. These timing parameters are
sample-tested only.
Symbol
Symbol
Table
51:
Minimum clock high time from clock pin
Minimum clock low time from clock pin
LE clear pulse width
LE preset pulse width
Clock high time
Clock low time
Write pulse width
Read pulse width
Setup time with global clock at IOE input register
Hold time with global clock at IOE input register
Clock-to-output delay with global clock at IOE output register C1 = 35 pF
Clock-to-output buffer disable delay
Clock-to-output buffer enable delay
Setup time with PLL clock at IOE input register
Hold time with PLL clock at IOE input register
Clock-to-output delay with PLL clock at IOE output register
PLL clock-to-output buffer disable delay
PLL clock-to-output buffer enable delay
Parameter
Note (1)
Parameter
Slow slew rate = OFF
C1 = 35 pF
Slow slew rate = OFF
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